• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.370-370
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• 2000

In this paper, we design a Multi-Fuzzy model by means of HCM clustering and genetic algorithms for a nonlinear system. In order to determine structure of the proposed Multi-Fuzzy model, HCM clustering method is used. The parameters of membership function of the Multi-Fuzzy ate identified by genetic algorithms. A aggregate performance index with a weighting factor is used to achieve a sound balance between approximation and generalization abilities of the model. We use simplified inference and linear inference as inference method of the proposed Multi-Fuzzy mode] and the standard least square method for estimating consequence parameters of the Multi-Fuzzy. Finally, we use some of numerical data to evaluate the proposed Multi-Fuzzy model and discuss about the usefulness.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.11
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• pp.637-642
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• 2000

IEEE 1149.1 boundary scan architecture is used as a standard in board-level system testing. The simplicity of this architecture is an advantage in system testing, but at the same time, it it makes a limitation of applications. Because of several problems such as 3-state net conflicts, or ambiguity issues, interconnect testing for multi-drop multi-board systems is more difficult than that of single board systems. A new approach using IEEE 1149.1 boundary scan architecture for multi-drop multi-board systems is developed in this paper. Adding boundary scan cells on backplane bus lines, each board has a complete scan-chain for interconnect test. This new scan-path insertion method on backplane bus using limited 1149.1 test bus less area overhead and mord efficient than previous approaches.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.129-132
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• 2019

This paper explains the design idea of a multi-Hop network for LoRaWAN. First, the existing LoRaWAN communication method(Single-Hop) will be described based on the standard specification. It then discusses technical considerations when converting from LoRaWAN to a multi-hop network. Finally, we introduce our ideas in this paper.

• Journal of the Korean Statistical Society
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• v.30 no.2
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• pp.327-345
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• 2001

New statistical methods are ended to analyzed data in a multi-scale way. Some multi-scale extensions of stand methods, including novel visualization using dynamic graphics are proposed. These tools are used to explore non-standard structure in internet traffic data.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.49 no.3
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• pp.74-80
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• 2012

Recently at SCIS2011, Nakatsu et. al. proposed multi-round Correlation Power Analysis(CPA) on Hardware Advanced Encryption Standard(AES) to improve the performance of CPA with limited number of traces. In this paper, we propose, Multi-Round CPA to retrieve master key using CPA of 1round and 2round on Hardware DES. From the simulation result for the proposed attack method, we could extract 56-bit master key using the 300 power traces of Hardware DES in DPA contes. And it was proved that we can search more master key using multi-round CPA than using single round CPA in limited environments.

• Journal of the Korean Society for Precision Engineering
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• v.26 no.11
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• pp.124-130
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• 2009

In the multi-stage shape drawing process, the most important aspect for the economy is the correct design of the various drawing stage. For most of the products commonly available round or square materials can be used as initial material. However, special products should be pre-rolled. This study proposes a process design method of multi-stage shape drawing process for producing cross roller guide. Firstly, a standard classification of shape drawing process is suggested based on the requirement of pre-rolling process. And a design method is proposed to design the intermediate die shape. The process design method is applied to design the multi-stage shape drawing process for producing cross roller guide. Finally, the effectiveness of the proposed design method is verified by FE-analysis and shape drawing experiment.

• Journal of information and communication convergence engineering
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• v.13 no.4
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• pp.235-240
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• 2015

A decimation chain for multi-standard reconfigurable radios is presented for 900-MHz and 1,900-MHz dual-band cellular standards with a data interpolator based on the Lagrange method for adjusting the variable data rate to a fixed data rate appropriate for each standard. The two proposed configurations are analyzed and compared to provide insight into aliasing and the signal bandwidth by means of a newly introduced measure called interpolation error. The average interpolation error is reduced as the ratio of the sampling frequency to the signal BW is increased. The decimation chain and the multi-rate analog-to-digital converter are simulated to compute the interpolation error and the output signal-to-noise ratio. Further, a method to operate the above-mentioned chain under a compressed mode of operation is proposed in order to guarantee continuous packet connectivity for inter-radio-access technologies. The presented decimation chain can be applied to LTE, WCDMA, GSM multi-mode multi-band digital front-end which will ultimately lead to the software-defined radio.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.9C
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• pp.589-595
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• 2011

This paper proposes an improved multi-stage timing offset estimation scheme for orthogonal frequency division multiplexing (OFDM) systems in multipath fading channel environment. The conventional multi-stage timing offset estimation scheme is very sensitive to the random multipath components. By exploiting the sample standard deviation of the cross-correlation values, the proposed scheme achieves a robustness to the random multipath components. Simulation results demonstrate that the proposed scheme has a higher correct estimation probability and has a better mean square error (MSE) performance than the conventional scheme in multipath fading channels.

• Journal of Korea Society of Digital Industry and Information Management
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• v.12 no.4
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• pp.81-87
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• 2016

Recently, as the heterogeneous network (HetNet) has been deployed widely to support various kinds of Radio Access Networks(RANs) with a combination of Macro, Pico, and/or Femto cells, research and standardization efforts have been very active regarding the concept of Licensed Shared Access (LSA) for supporting spectrum sharing. In order for a mobile device to efficiently support the spectrum sharing, the mobile device shall be reconfigurable, meaning that its radio application code has to be adaptively changed in accordance with the hopping of desired spectral band. Especially, Working Group 2 (WG2) of Technical Committee (TC) Reconfigurable Radio System (RRS) of European Telecommunications Standards Institute (ETSI) has been a main driving force for developing standard architecture for Multi-mode Mobile Device (MD) that can be applied to the LSA system. In this paper, we introduce the Multi-mode MD architecture for supporting LSA-based spectrum sharing. An implementation of a test-bed of Multi-mode MD is presented in order to verify the feasibility of the standard MD architecture for the purpose of LSA-based spectrum sharing through various experimental tests.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.148-151
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• 2005

This paper proposes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that convert redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was designed using a 0.35${\mu}m$ standard CMOS Process. Proposed demultiplexer is achieved an operating speed of 3Gb/s with a supply voltage of 3.3V and with power consumption of 48mW. Designed circuit is limited by maximum operating frequency of process. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 3Gb/s in submicron process of high of operating frequency.