• Aerospace Engineering and Technology
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• v.11 no.2
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• pp.171-181
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• 2012

As a sub-system of an air traffic control system, SDP(Surveillance Data Processor) provides with the system tracks of aircraft using the surveillance sensor data from various air traffic surveillance sensors, such as radars. Therefore, the high accuracy of tracking results is a crucial requirement for safe flights, and verification of the required system performance of SDP is an essential step in development. Moreover, the quantitative evaluation of target tracking accuracy is important for newly developed SDP, since there are several tracking methods for Multi-Sensor Multi-Target Tracking, such as MRT(Multi Radar Tracking), inevitably required as the main function of SDP. In this study, definition of required system performances, establishment of test environment, and test results for MRT performance evaluation of SDP, which is being developed in KARI(Korea Airspace Research Institute) are presented.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.791-794
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• 2003

The increasing computational capability of processors is driving the need for high bandwidth links to communicate and store the information that is processed. Such links are often an important part of multi processor interconnection, processor-to-memory interfaces and Serial-network interfaces. This paper describes a 0.11-${\mu}{\textrm}{m}$ CMOS 4 Gbp s/pin 3-Level transceiver using RSL/(Rambus Signaling Logic) for high bandwidth. This system which uses a high-gain windowed integrating receiver with wide common-mode range which was designed in order to improve SNR when operating with the smaller input overdrive of 3-Level. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by low pass effects of channel, process-limited on-chip clock frequency, and serial link distance. In order to detect the transmited 4Gbps/pin with 3-Level data sucessfully ,the receiver is designed using 3-stage sense amplifier. The proposed transceiver employes multi-level signaling (3-Level Pulse Amplitude Modulation) using clock multi phase, double data rate and Prbs patten generator. The transceiver shows data rate of 3.2 ~ 4.0 Gbps/pin with a 1GHz internal clock.

• 제어로봇시스템학회:학술대회논문집
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• 1988.10a
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• pp.507-510
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• 1988

The main subject of this paper is the development of new ROBOT CONTROLLER, which can support MULTI-TASKING and MULTI-ROBOT functions. The system consists of various kinds of CPU modules according to their independent jobs. Acceleration and Deceleration profile is given in order to achieve the smooth robot motion and high cycle time. Further the communication capacity should be upgraded to meet the various kinds of peripheral PA devices.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1985.10a
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• pp.129-133
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• 1985

• Journal of Korea Multimedia Society
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• v.1 no.2
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• pp.154-161
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• 1998

This paper proposes a parallel processor system which processes cultural assets image recognition and retrieval algorithm in real time. A serial algorithm which is developed for the parallel processor system is parallellized. The parallel processor system consists of a control unit, 100 PE(Processing Elements), and 10 Park's multi-access memory systems which has 11 memory modules per each one. The parallel processor system is simulated by CADENCE Verilog-XL which is a package for the hardware simulation. With the same simulated results as that of the serial algorithm, the speed ratio of the parallel algorithm to the serial one is 81. The parallel processor system we proposed is quite effective for cultural assets image processing.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.1
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• pp.99-105
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• 2021

Today, a superscalar processor is the basic unit or an essential component of a multi-core processor, SoCs, and GPUs. Hence, a high-performance out-of-order superscalar processor must be adopted for these systems to maximize its performance. The superscalar processor fetches, issues, executes, and writes back multiple instructions per cycle by utilizing reorder buffers and reservation stations to dynamically schedule instructions in a pipelined scheme. In this paper, a fully pipelined out-of-order superscalar processor with speculative execution is designed with VHDL and verified with GHDL. As a result of the simulation, the program composed of ARM instructions is successfully performed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.101-109
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• 2017

This paper presents a high-throughput low-complexity 512-point eight-parallel mixed-radix multipath delay feedback (MDF) fast Fourier transform (FFT) processor architecture for orthogonal frequency division multiplexing (OFDM) applications. To decrease the number of twiddle factor (TF) multiplications, a mixed-radix $2^4/2^3$ FFT algorithm is adopted. Moreover, a dual-path shared canonical signed digit (CSD) complex constant multiplier using a multi-layer scheme is proposed for reducing the hardware complexity of the TF multiplication. The proposed FFT processor is implemented using TSMC 90-nm CMOS technology. The synthesis results demonstrate that the proposed FFT processor can lead to a 16% reduction in hardware complexity and higher throughput compared to conventional architectures.

• Journal of Advanced Marine Engineering and Technology
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• v.30 no.2
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• pp.311-318
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• 2006

In this study, the performance tests for single and dual micro processor configurations are performed to investigate how the accelerated OpenGL components and applications are dependent on processor configurations. At present, many major providers of the engineering graphics workstations have recommended that multiprocessors are better than single processor. However, we confirmed that the single processor configuration is more faster and more effective than competitive configurations and suggested the economic method to improve the performance of the engineering graphics workstations.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.11a
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• pp.42-45
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• 2012

A network processor (NP) is an application-specific instruction-set processor for fast and efficient packet processing. There are many issues in compiler's code generation and optimization due to NP's hardware constraints and special hardware support. In this paper, we describe in detail how to resolve the issues. Our compiler was developed on LLVM 3.0 and the NP target was our in-house network processor which consists of 32 64-bit RISC processors and supports multi-context with special hardware structures. Our compiler incurs only 9.36% code size overhead over hand-written code while satisfying QoS, and the generated code was tested on a real packet processing hardware, called S20 for code verification and performance evaluation.

• The Journal of the Acoustical Society of Korea
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• v.40 no.5
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• pp.523-529
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• 2021

In this paper, we designed and developed an Emotional Speech Synthesis Markup Language (SSML) processor. Multi-speaker emotional speech synthesis technology that can express multiple voice colors and emotional expressions have been developed, and we designed Emotional SSML by extending SSML for multiple voice colors and emotional expressions. The Emotional SSML processor has a graphic user interface and consists of following four components. First, a multi-speaker emotional text editor that can easily mark specific voice colors and emotions on desired positions. Second, an Emotional SSML document generator that creates an Emotional SSML document automatically from the result of the multi-speaker emotional text editor. Third, an Emotional SSML parser that parses the Emotional SSML document. Last, a sequencer to control a multi-speaker and emotional Text-to-Speech (TTS) engine based on the result of the Emotional SSML parser. Based on SSML which is a programming language and platform independent open standard, the Emotional SSML processor can easily integrate with various speech synthesis engines and facilitates the development of multi-speaker emotional text-to-speech applications.