• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1730-1732
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• 2002

This paper proposes a multi-color lamp using ROB LEDs for color variation. The lamp has an internal controller circuit. so it can be directly connected to the existing incandescent lamp socket. It's main body is comprised of two PCB layers. The upper layer contains 44 LEDs and the lower one has a simple microcontroller-based PWM control circuit. Appropriate number of RGB LEDs are so chosen according to the color mixing theory that the overall LEDs represent a color temperature of 6500K. The lamp has functions of both ON/OFF control and PWM control, so is capable of color variation of over 100,000 colors and of more than 10 patterns.

• Proceedings of the KIEE Conference
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• 2001.11a
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• pp.35-37
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• 2001

다층 인쇄 회로 기판에 Combline 구조를 가진 스트립 라인 또는 마이크로 스트립 라인 대역통과 필터를 구현하였다. 저 비용 구현과 이동성과 휴대성을 강조하기 위해 기존의 세라믹 대신 FR4 와 에폭시를 기반으로 하는 다층 회로 기판의 도체 층에 집적화하였다. Combline 각 끝단에 커패시터를 부하 함으로써 전기적 길이를 화장하였고 전체적인 크기를 감소시킴으로서 적당한 필터 특성을 얻을 수 있었다. 구현된 필터는 마이크로파 대역에서 사용 가능하며 특히 Bluetooth나 Wireless LAN 과 같은 ISM 대역을 사용하는 무선통신소자로서 사용 가능하다.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.1
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• pp.35-42
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• 2003

Differential signaling has become a popular choice for high-speed interconnection schemes on Printed Circuit Boards (PCBs), offering superior immunity to external noise. However, conventional differential transmission lines on PCBs have problems, such as crosstalk and radiated emission. To overcome these, we propose a Twisted Differential Line (TDL) structure on a multi-layer PCB. Its improved immunity to crosstalk noise and the reduced radiated emission has been successfully demonstrated by measurement. The proposed structure is proven to transmit 3 Gbps digital signals with a clear eye-pattern. Furthermore, it is subject to much less crosstalk noise and achieves a 13 dB suppression of radiated emission. Index Terms - Twisted Differential Line, Differential Signaling, Crosstalk, Radiated Emission, Transmission Line, Twisted Pair

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2012.11a
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• pp.71-71
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• 2012

Memory 반도체 Test공정에서 사용되는 Probe Card의 Probing Area가 넓어지면서 종래에 사용되던 Cantilever제품의 사용이 불가능하게 되고, MEMS공정을 사용한 새로운 형태의 Advanced제품이 시장에 출현을 하였다. MEMS형의 제품은 다수의 Micro Spring을 MLC(Multi Layer Ceramic)위에 MEMS 공정을 사용하여 생성하는 방식으로서 MLC는 좁은 지역에 다수의 Pin을 생성 할 수 있는 공간을 만들어 주며, 또 다른 이유는 전기적 특성인 임피던스를 맞추고 다수의 Pin의 압력에 의하여 생기는 하중을 Ceramic기판으로 지탱하기 위한 목적도 있다. 이에 MLC와 같은 전기적 특성을 임피던스를 맞춘 RF-CPCB를 사용하여 작은 면적에 다수의 Pin접합이 가능한 방법을 마련한 후, 이 RF-PCB를 부착하여 Pin의 하중을 받는 Wafer와 유사한 열팽창을 갖는 Substrate를 사용하여 MLC를 대체하여 다양한 온도 조건에서 사용이 가능하며, 복잡하고 공정비가 많이 드는 MEMS 공정에 의한 일괄 Micro Spring 생성 공정을 전주 도금 또는 2D방식의 도금 Pin으로 대체하였으며, Probe Card의 중요한 물리적 특성인 Pin들의 정렬도를 마련하기 위해 Photo Process를 사용한 Wafer로 만든 Wafer Pin Array Frame을 사용하여 2D 제작 Pin을 일괄 또는 부분 접합이 가능한 방법으로 Probe Array Head를 제작하여 이들을 부착하여 Probe Array Head를 이전의 MEMS공정 방법에 비해 쉽고 빠르게 만들어 probe Card를 제작 할 수 있게 되었다.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.7-15
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• 2012

Semiconductor packages are increasingly moving toward miniaturization, lighter and multi-functions for mobile application, which requires highly integrated multi-stack package. To meet the industrial demand, the package and silicon chip become thinner, and ultra-thin packages will show serious reliability problems such as warpage, crack and other failures. These problems are mainly caused by the mismatch of various package materials and geometric dimensions. In this study we perform the numerical analysis of the warpage deformation and thermal stress of 4-layer stacked FBGA package after EMC molding and reflow process, respectively. After EMC molding and reflow process, the package exhibits the different warpage characteristics due to the temperature-dependent material properties. Key material properties which affect the warpage of package are investigated such as the elastic moduli and CTEs of EMC and PCB. It is found that CTE of EMC material is the dominant factor which controls the warpage. The results of RSM optimization of the material properties demonstrate that warpage can be reduced by $28{\mu}m$. As the silicon die becomes thinner, the maximum stress of each die is increased. In particular, the stress of the top die is substantially increased at the outer edge of the die. This stress concentration will lead to the failure of the package. Therefore, proper selection of package material and structural design are essential for the ultra-thin die packages.

• Journal of Electrical Engineering and Technology
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• v.13 no.4
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• pp.1638-1643
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• 2018

Multi-layer ceramic capacitors as decoupling capacitor were fabricated by dielectric composition with a high dielectric constant. The fabricated decoupling capacitors were embedded in the PCB of the 10G RF transceiver module and evaluated for the characteristics of electrical noise by the level of AC input voltage. In order to further improve the electrical properties of the $BaTiO_3$ based composite, glass frit, MgO, $Y_2O_3$, $Mn_3O$, $V_2O_5$, $BaCO_3$, $SiO_2$, and $Al_2O_3$ were used as additives. The electrical properties of the composites were determined by various amounts of additives and optimum sintering temperature. As a result of the optimized composite, it was possible to obtain a density of $5.77g/cm^3$, a dielectric constant of 1994, and an insulation resistance of $2.91{\times}10^{12}{\Omega}$ at an additive content of 5wt% and a sintering temperature of $1250^{\circ}C$. After forming a $2.5{\mu}m$ green sheet using the doctor blade method, a total of 77 layers were laminated and sintered at $1180^{\circ}C$. A decoupling capacitor with a size of $0.6mm(W){\times}0.3mm(L){\times}0.3mm(T)$ (width, length and thickness, respectively) and a capacitance of 100 nF was embedded using a PCB process for the 10G RF Transceiver modules. In the range of AC input voltage 400mmV @ 500kHz to 2200mV @ 900kHz, the embedded 10G RF Transceiver modules evaluated that it has better electrical performance than the non-embedded modules.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.16-22
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• 2013

A general characterization procedure based on the extraction of a 2n-port admittance matrix corresponding to n uniform coupled lines on the multi-layered substrate using the Finite-Difference Time-Domain (FDTD) technique is presented. In this paper, the frequency-dependent normal mode parameters are obtained from the 2n-port admittance matrix to analyze multi-layered asymmetric coupled line structure, which in turn provides the frequency-dependent propagation constant, effective dielectric constant, and line-mode characteristic impedances. To illustrate the technique, several practical coupled line structures on multi-layered substrate have been simulated. Especially, embedded conductor structures have been simulated. Comparisons with Spectral Domain Method are given, and their results agree well. It is shown that the FDTD based time domain characterization procedure is an excellent broadband simulation tool for the design of multiconductor coupled lines on multilayered PCBs as well as thick or thin hybrid structures.

• Journal of IKEEE
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• v.26 no.3
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• pp.456-461
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• 2022

In this paper, a two-stage single-ended power amplifier (PA) with broadband gain characteristics was presented by utilizing a radio frequency (RF) transformer (TF), which is essential for a differential amplifier. The bandwidth of a PA can be improved by designing TF to have broadband characteristics and then applying it to the inter-stage matching network (IMN) of a PA. For broadband gain characteristics while maintaining the performance and area of the existing PA, an IMN was implemented on an monolithic microwave integrated circuit (MMIC) and a multi-layer printed circuit board (PCB), and the simulation results were compared. As a result of simulating the PA module designed using InGaP/GaAs HBT model, it has been confirmed that the PA employing the proposed design method has an improved fractional bandwidth of 19.8% at a center frequency of 3.3GHz, while the conventional PA showed that of 11.2%.

• Analytical Science and Technology
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• v.22 no.6
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• pp.449-457
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• 2009

Total PCBs (62 congeners) has been determined in the retailed foods by the isotopic dilution method and the exposure assessment has been performed. Put into a food sample $^{13}C$-labeled standard for recovery was added and then it was extracted, cleaned-up by multi-layer column chromatography and then analyzed by HRGC/MS. The average levels (ng/g) detected was 0.1 for rice, 1.8~3.4 for meats, 0.3~3.7 for milk and dairy products, 10.0 for egg and 0.8~34.4 for fishes. Distribution of total PCBs was in order of fishes (94.4%) > meats (2.3%) > eggs (1.7%) > milk and dairy products (1.3%) > rice (0.3%). The estimated daily intake(EDI) was 14 ng/kg bw/day. It was concluded that there was no health risk at all.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.55-67
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• 2010

The electrical properties of a back drilled via-hole (BDH) without the open-stub and the plated through via-hole (PTH) with the open-stub, which is called the conventional structure, in a high-count multi~layered (HCML) printed circuit board (PCB) were investigated for a high-speed digital system, and a selected inner layer to transmit a high-speed signal was farthest away from the side to mount the component. Within 10 GHz of the broadband frequency, a design of experiment (DOE) methodology was carried out with three cause factors of each via-hole structure, which were the distance between the via-holes, the dimensions of drilling pad and the anti-pad in the ground plane, and then the relation between cause and result factors which were the maximum return loss, the half-power frequency, and the minimum insertion loss was analyzed. Subsequently, the empirical formulae resulting in a macro model were extracted and compared with the experiment results. Even, out of the cause range, the calculated results obtained from the macro model can be also matched with the measured results within 5 % of the error.