• Title/Summary/Keyword: modified Booth 알고리즘

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FPGA Implementation of High Speed RSA Cryptosystem Using Radix-4 Modified Booth Algorithm and CSA (Radix-4 Modified Booth 알고리즘과 CSA를 이용한 고속 RSA 암호시스템의 FPGA 구현)

  • 박진영;서영호;김동욱
    • Proceedings of the IEEK Conference
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    • 2001.06a
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    • pp.337-340
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    • 2001
  • This paper presented a new structure of RSA cryptosystem using modified Montgomery algorithm and CSA(Carry Save Adder) tree. Montgomery algorithm was modified to a radix-4 modified Booth algorithm. By appling radix-4 modified Booth algorithm and CSA tree to modular multiplication, a clock cycle for modular multiplication has been reduced to (n+3)/2 and carry propagation has been removed from the cell structure of modular multiplier. That is, the connection efficiency of full adders is enhanced.

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High-performance Pipeline Architecture for Modified Booth Multipliers (Modified Booth 곱셈기를 위한 고성능 파이프라인 구조)

  • Kim, Soo-Jin;Cho, Kyeong-Soon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.12
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    • pp.36-42
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    • 2009
  • This paper proposes the high-performance pipeline architecture for modified Booth multipliers. The proposed multiplier circuits are based on modified Booth algorithm and pipeline architecture which are the most widely used techniques to accelerate the multiplication speed. In order to implement the optimally pipelined multipliers, many kinds of experiments have been conducted. The experimental results show that the speed improvement gain exceeds the area penalty and this trend is manifested as the number of pipeline stages increases. It is also important to insert the pipeline registers at the proper positions. We described the proposed modified Booth multiplier circuits in Verilog HDL and synthesized the gate-level circuits using 0.13um standard cell library. The resultant multiplier circuits show better performance than others. Since they operate at GHz ranges, they can be used in the application systems requiring extremely high performance such as optical communication systems.

Low-power Horizontal DA Filter Structure Using Radix-16 Modified Booth Algorithm (Radix-16 Modified Booth 알고리즘을 이용한 저전력 Horizontal DA 필터 구조)

  • Shin, Ji-Hye;Jang, Young-Beom
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.47 no.12
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    • pp.31-38
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    • 2010
  • In tins paper, a new DA(Distributed Arithmetic) tilter implementation technique has been proposed. Contrary to vertical directional calculation of input sample bit format in the conventional DA implementation technique, proposed implementation technique utilizes horizontal directional calculation of input sample bit format. Since proposed technique calculates in horizontal direction, it does not need ROM and utilizes the Modified Booth algorithm. Furthermore proposed technique can be applied to implement the variable coefficients filters in addition to the fixed coefficients filters. Using conventional and proposed techniques, a 20 tap filter is implemented by Verilog-HDL coding. Through Synopsis synthesis tool, it has been shown that 41.6% area reduction can be achieved.

A Study on the IC, Implementation of High Speed Multiplier for Real Time Digital Signal Processing (실시간 디지털 신호 처리용 고속 MULTIPLIER 단일칩화에 관한 연구)

  • 문대철;차균현
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.15 no.7
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    • pp.628-637
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    • 1990
  • In this paper we present on architecture for a high sppeed CMOS multiplier which can be used for real-time digital signal processing. And a synthesis method for designing highly parallel algorithms in VLSI is presented. A parallel multiplier design based on the modified Booth's algorithms and Ling's algorthm. This paper addresses the design of multiplier capable of accpting data in 2's complement notation and coefficients in 2's complement notation. Multiplier consists of an interative array of sequential cells, and are well suited to VLSI implementation as a results of their modularity and regularity. Booth's decoders can be fully tested using a relatively small number af test vector.

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Design of a 323${\times}$2-Bit Modified Booth Multiplier Using Current-Mode CMOS Multiple-Valued Logic Circuits (전류모드 CMOS 다치 논리회로를 이용한 32${\times}$32-Bit Modified Booth 곱셈기 설계)

  • 이은실;김정범
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.12
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    • pp.72-79
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    • 2003
  • This paper proposes a 32${\times}$32 Modified Booth multiplier using CMOS multiple-valued logic circuits. The multiplier based on the radix-4 algorithm is designed with current mode CMOS quaternary logic circuits. Designed multiplier is reduced the transistor count by 67.1% and 37.3%, compared with that of the voltage mode binary multiplier and the previous multiple-valued logic multiplier, respectively. The multiplier is designed with a 0.35${\mu}{\textrm}{m}$ standard CMOS technology at a 3.3V supply voltage and unit current 10$mutextrm{A}$, and verified by HSPICE. The multiplier has 5.9㎱ of propagation delay time and 16.9mW of power dissipation. The performance is comparable to that of the fastest binary multiplier reported.

Elliptic Curve Scalar Point Multiplication Using Radix-4 Modified Booth's Algorithm (Radix-4 Modified Booth's 알고리즘을 응용한 타원곡선 스칼라 곱셈)

  • 문상국
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.6
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    • pp.1212-1217
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    • 2004
  • The main back-bone operation in elliptic curve cryptosystems is scalar point multiplication. The most frequently used method implementing the scalar point multiplication, which is performed in the upper level of GF multiplication and GF division, has been the double-and-add algorithm, which is recently challenged by NAF(Non-Adjacent Format) algorithm. In this paper, we propose a more efficient and novel scalar multiplication method than existing double-and-add by applying redundant receding which originates from radix-4 Booth's algorithm. After deriving the novel quad-and-add algorithm, we created a new operation, named point quadruple, and verified with real application calculation to utilize it. Derived numerical expressions were verified using both C programs and HDL (Hardware Description Language) in real applications. Proposed method of elliptic curve scalar point multiplication can be utilized in many elliptic curve security applications for handling efficient and fast calculations.

A Efficient Architecture of MBA-based Parallel MAC for High-Speed Digital Signal Processing (고속 디지털 신호처리를 위한 MBA기반 병렬 MAC의 효율적인 구조)

  • 서영호;김동욱
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.7
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    • pp.53-61
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    • 2004
  • In this paper, we proposed a new architecture of MAC(Multiplier-Accumulator) to operate high-speed multiplication-accumulation. We used the MBA(Modified radix-4 Booth Algorithm) which is based on the 1's complement number system, and CSA(Carry Save Adder) for addition of the partial products. During the addition of the partial product, the signed numbers with the 1's complement type after Booth encoding are converted in the 2's complement signed number in the CSA tree. Since 2-bit CLA(Carry Look-ahead Adder) was used in adding the lower bits of the partial product, the input bit width of the final adder and whole delay of the critical path were reduced. The proposed MAC was applied into the DWT(Discrete Wavelet Transform) filtering operation for JPEG2000, and it showed the possibility for the practical application. Finally we identified the improved performance according to the comparison with the previous architecture in the aspect of hardware resource and delay.

Design of a 64×64-Bit Modified Booth Multiplier Using Current-Mode CMOS Quarternary Logic Circuits (전류모드 CMOS 4치 논리회로를 이용한 64×64-비트 변형된 Booth 곱셈기 설계)

  • Kim, Jeong-Beom
    • The KIPS Transactions:PartA
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    • v.14A no.4
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    • pp.203-208
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    • 2007
  • This paper proposes a $64{\times}64$ Modified Booth multiplier using CMOS multi-valued logic circuits. The multiplier based on the radix-4 algorithm is designed with current mode CMOS quaternary logic circuits. Designed multiplier is reduced the transistor count by 64.4% compared with the voltage mode binary multiplier. The multiplier is designed with Samsung $0.35{\mu}m$ standard CMOS process at a 3.3V supply voltage and unit current $5{\mu}m$. The validity and effectiveness are verified through the HSPICE simulation. The voltage mode binary multiplier is achieved the occupied area of $7.5{\times}9.4mm^2$, the maximum propagation delay time of 9.8ns and the average power consumption of 45.2mW. This multiplier is achieved the maximum propagation delay time of 11.9ns and the average power consumption of 49.7mW. The designed multiplier is reduced the occupied area by 42.5% compared with the voltage mode binary multiplier.

Design of a Multi-Valued Arithmetic Processor with Encoder and Decoder (인코더, 디코오더를 가지는 다치 연산기 설계)

  • 박진우;양대영;송홍복
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.2 no.1
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    • pp.147-156
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    • 1998
  • In this paper, an arithmetic processor using multi-valued logic is designed. For implementing of multi-valued logic circuits, we use current-mode CMOS circuits and design encoder which change binary voltage-mode signals to multi-valued current-mode signals and decoder which change results of arithmetic to binary voltage-mode signals. To reduce the number of partial product we use 4-radix SD number partial product generation algorithm that is an extension of the modified Booth's algorithm. We demonstrate the effectiveness of the proposed arithmetic circuits through SPICE simulation and Hardware emulation using FPGA chip.

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A Design of the High-Speed Cipher VLSI Using IDEA Algorithm (IDEA 알고리즘을 이용한 고속 암호 VLSI 설계)

  • 이행우;최광진
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.11 no.1
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    • pp.64-72
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    • 2001
  • This paper is on a design of the high-speed cipher IC using IDEA algorithm. The chip is consists of six functional blocks. The principal blocks are encryption and decryption key generator, input data circuit, encryption processor, output data circuit, operation mode controller. In subkey generator, the design goal is rather decrease of its area than increase of its computation speed. On the other hand, the design of encryption processor is focused on rather increase of its computation speed than decrease of its area. Therefore, the pipeline architecture for repeated processing and the modular multiplier for improving computation speed are adopted. Specially, there are used the carry select adder and modified Booth algorithm to increase its computation speed at modular multiplier. To input the data by 8-bit, 16-bit, 32-bit according to the operation mode, it is designed so that buffer shifts by 8-bit, 16-bit, 32-bit. As a result of simulation by 0.25 $\mu\textrm{m}$ process, this IC has achieved the throughput of 1Gbps in addition to its small area, and used 12,000gates in implementing the algorithm.