• The Transactions of the Korean Institute of Power Electronics
• /
• v.16 no.5
• /
• pp.440-447
• /
• 2011

This paper deals with supercapacitor energy storage system for the compensation of the slow response characteristics of a fuel cell generation system for grid connection. A bidirectional dc/dc converter is used for the charging and discharging of the supercapacitor. The conventional converters use additional clamping circuit, etc. to reduce a voltage spike at the instant of switching and to provide wide range of soft switching. The proposed method provides simplified hardware implementation without any clamping circuit, and soft switching condition for both charging and discharging mode with proper switching patterns. The usefulness of the proposed scheme is verified through simulation and experimental results with 1 kW system.

• Journal of the Korea Society of Computer and Information
• /
• v.28 no.12
• /
• pp.221-229
• /
• 2023

Recently, Grid-forming(GFM) converter, which offers features such as virtual inertia, damping, black start capability, and islanded mode operation in power systems, has gained significant attention. However, in low-voltage microgrids(MG), it faces challenges due to the coupling phenomenon between active and reactive power caused by the low line impedance X/R ratio and a non-negligible power angle. This power coupling issue leads to stability and performance degradation, inaccurate power sharing, and control parameter design problems for GFM converters. Therefore, this paper serves as a review study on not only control methods associated with GFM converters but also power decoupling techniques. The aim is to introduce promising control methods and enhance accessibility to future research activities by providing a critical review of power decoupling methods. Consequently, by facilitating easy access for future researchers to the study of power decoupling methods, this work is expected to contribute to the expansion of distributed power generation.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.42 no.2
• /
• pp.432-443
• /
• 2017

The primary goal of the MPEG-H 3D Audio standard is to provide immersive audio environments for high-resolution broadcasting services such as UHDTV. This standard incorporates a wide range of technologies such as encoding/decoding technology for multi-channel/object/scene-based signal, rendering technology for providing 3D audio in various playback environments, and post-processing technology. The reference software decoder of this standard is a structure combining several modules and can operate in various modes. Each module is composed of independent executable files and executed sequentially, real time decoding is impossible. In this paper, we make DLL library of the core decoder, format converter, object renderer, and binaural renderer of the standard and integrate them to enable frame-based decoding. In addition, by measuring the computation complexity of each mode of the MPEG-H 3D-Audio decoder, this paper also provides a reference for selecting the appropriate decoding mode for various hardware platforms. As a result of the computational complexity measurement, the low complexity profiles included in Korean broadcasting standard has a computation complexity of 2.8 times to 12.4 times that of the QMF synthesis operation in case of rendering as a channel signals, and it has a computation complexity of 4.1 times to 15.3 times of the QMF synthesis operation in case of rendering as a binaural signals.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.21 no.10
• /
• pp.1169-1176
• /
• 2010

The RF front-end for L1/L2 dual-band Global Positioning System(GPS) receiver is presented in this paper. The RF front-end(down-converter) using low IF architecture consists of a wideband low noise amplifier(LNA), a current mode logic(CML) frequency divider and a I/Q down-conversion mixer with a poly-phase filter for image rejection. The current bleeding technique is used in the LNA and mixer to obtain the high gain and solve the head-room problem. The common drain feedback is adopted for low noise amplifier to achieve the wideband input matching without inductors. The fabricated RF front-end using $0.18{\mu}m$ CMOS process shows a gain of 38 dB for L1 and 41 dB for L2 band. The measured IIP3 is -29 dBm in L1 band and -33 dBm in L2 band, The input return loss is less than -10 dB from 50 MHz to 3 GHz. The measured noise figure(NF) is 3.81 dB for L1 band and 3.71 dB for L2 band. The image rejection ratio is 36.5 dB. The chip size of RF front end is $1.2{\times}1.35mm^2$.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.14 no.2
• /
• pp.309-316
• /
• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.44 no.5
• /
• pp.62-70
• /
• 2007

In this paper, the boost Power Factor Correction(PFC) technique for Direct Torque Control(DTC) of brushless DC motor drive in the constant torque region is implemented on a TMS320F2812DSP. Unlike conventional six-step PWM current control, by properly selecting the inverter voltage space vectors of the two-phase conduction mode from a simple look-up table at a predefined sampling time, the desired quasi-square wave current is obtained, therefore a much faster torque response is achieved compared to conventional current control. Furthermore, to eliminate the low-frequency torque oscillations caused by the non-ideal trapezoidal shape of the actual back-EMF waveform of the BLDC motor, a pre-stored back-EMF versus position look-up table is designed. The duty cycle of the boost converter is determined by a control algorithm based on the input voltage, output voltage which is the dc-link of the BLDC motor drive, and inductor current using average current control method with input voltage feed-forward compensation during each sampling period of the drive system. With the emergence of high-speed digital signal processors(DSPs), both PFC and simple DTC algorithms can be executed during a single sampling period of the BLDC motor drive. In the proposed method, since no PWM algorithm is required for DTC or BLDC motor drive, only one PWM output for the boost converter with 80 kHz switching frequency is used in a TMS320F2812 DSP. The validity and effectiveness of the proposed DTC of BLDC motor drive scheme with PFC are verified through the experimental results. The test results verify that the proposed PFC for DTC of BLDC motor drive improves power factor considerably from 0.77 to as close as 0.9997 with and without load conditions.

• Journal of Power Electronics
• /
• v.11 no.4
• /
• pp.408-417
• /
• 2011

The plug-in hybrid electric vehicles (PHEVs) are specialized hybrid electric vehicles that have the potential to obtain enough energy for average daily commuting from batteries. The PHEV battery would be recharged from the power grid at home or at work and would thus allow for a reduction in the overall fuel consumption. This paper proposes an integrated power electronics interface for PHEVs, which consists of a novel Eight-Switch Inverter (ESI) and an interleaved DC/DC converter, in order to reduce the cost, the mass and the size of the power electronics unit (PEU) with high performance at any operating mode. In the proposed configuration, a novel Eight-Switch Inverter (ESI) is able to function as a bidirectional single-phase AC/DC battery charger/ vehicle to grid (V2G) and to transfer electrical energy between the DC-link (connected to the battery) and the electric traction system as DC/AC inverter. In addition, a bidirectional-interleaved DC/DC converter with dual-loop controller is proposed for interfacing the ESI to a low-voltage battery pack in order to minimize the ripple of the battery current and to improve the efficiency of the DC system with lower inductor size. To validate the performance of the proposed configuration, the indirect field-oriented control (IFOC) based on particle swarm optimization (PSO) is proposed to optimize the efficiency of the AC drive system in PHEVs. The maximum efficiency of the motor is obtained by the evaluation of optimal rotor flux at any operating point, where the PSO is applied to evaluate the optimal flux. Moreover, an improved AC/DC controller based Proportional-Resonant Control (PRC) is proposed in order to reduce the THD of the input current in charger/V2G modes. The proposed configuration is analyzed and its performance is validated using simulated results obtained in MATLAB/ SIMULINK. Furthermore, it is experimentally validated with results obtained from the prototypes that have been developed and built in the laboratory based on TMS320F2808 DSP.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.11
• /
• pp.83-94
• /
• 2003

In this paper. a highly linear and low glitch CMOS current mode digital-to-analog converter (DAC) by self calibration bias circuit is proposed. The architecture of the DAC is based on a current steering 6＋4 segmented type and new switching scheme for the current cell matrix, which reduced non-linearity error and graded error. In order to achieve a high performance DAC . novel current cell with a low spurious deglitching circuit and a new inverse thermometer decoder are proposed. The prototype DAC was implemented in a 0.35${\mu}{\textrm}{m}$ n-well CMOS technology. Experimental result show that SFDR is 60 ㏈ when sampling frequency is 32MHz and DAC output frequency is 7.92MHz. The DAC dissipates 46 mW at a 3.3 Volt single power supply and occupies a chip area of 1350${\mu}{\textrm}{m}$ ${\times}$750${\mu}{\textrm}{m}$.

• Journal of Sensor Science and Technology
• /
• v.23 no.5
• /
• pp.332-336
• /
• 2014

In this paper, we propose a complementary metal oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) PMOSFET-type photodetector for high-speed operation. The GBT photodetector of an active pixel sensor (APS) consists of a floating gate ($n^+$-polysilicon) tied to the body (n-well) of the PMOSFET. The p-n junction photodiode that is used in a conventional APS has a good dynamic range but low photosensitivity. On the other hand, a high-gain GBT photodetector has a high level of photosensitivity but a narrow dynamic range. In addition, the pixel size of the GBT photodetector APS is less than that of the conventional photodiode APS because of its use of a PMOSFET-type photodetector, enabling increased image resolution. A CMOS binary image sensor can be designed with simple circuits, as a complex analog to digital converter (ADC) is not required for binary processing. Because of this feature, the binary image sensor has low power consumption and high speed, with the ability to switch back and forth between a binary mode and an analog mode. The proposed CMOS binary image sensor was simulated and designed using a standard CMOS $0.18{\mu}m$ process.

• Journal of Applied Reliability
• /
• v.18 no.1
• /
• pp.66-71
• /
• 2018

Purpose: Performance recovered from SCR through cleaning was studied, measuring differential pressure, NOx reduction efficiency, fuel consumption and engine power before and after cleaning. Ideal cleaning intervals are proposed based on SCR mileage and differential pressure. SCR endurance and reliability improvements through cleaning were studied through physicochemical testing of SCR durability at 43,000km 50,000km, and 110,000km respectively. Methods: Engine power, fuel consumption and exhaust gas were measured using engine full load tests and ND-13 MODE by installing the SCR before cleaned at total engine mileages of 400,000 km, 300,000km and 200,000km. The same tests were performed after cleaning the SCR catalytic converter. Endurance and reliability of the SCR cleaning was studied through the same test by SCR catalyst after each 43,000km 50,000km, 110,000km, durability test on SCR cleaning. Conclusion: We confirmed the low-performance of the SCR due to clogging is restored by SCR cleaning technology. The NOx reduction efficiency was restored to 82%, 86% and 88% from 69%, 72% and 79%. As well as the NOx reduction efficiency, it was confirmed that the engine power, fuel consumption and back pressure was restored to fresh SCR levels. As a result of the durability and reliability achieved through SCR cleaning, we confined the appearance and reduction efficiency through visual inspection and ND-13 MODE are similar to new SCR catalysts. Finally, it was judged that there was no change in performance even when driving the SCR without cleaning throughout the 100,000 km mileage warranty.