• ETRI Journal
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• v.35 no.1
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• pp.41-50
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• 2013

Network Mobility (NEMO) handles mobility of multiple nodes in an aggregate manner as a mobile network. The standard NEMO suffers from a number of limitations, such as inefficient routing and increased handoff latency. Most previous studies attempting to solve such problems have imposed an extra signaling load and/or modified the functionalities of the main entities. In this paper, we propose a more secure and lightweight route optimization (RO) mechanism based on exploiting the firewall in performing the RO services on behalf of the correspondent nodes (CNs). The proposed mechanism provides secure communications by making an authorized decision about the mobile router (MR) home of address, MR care of address, and the complete mobile network prefixes underneath the MR. In addition, it reduces the total signaling required for NEMO handoffs, especially when the number of mobile network nodes and/or CNs is increased. Moreover, our proposed mechanism can be easily deployed without modifying the mobility protocol stack of CNs. A thorough analytical model and network simulator (Ns-2) are used for evaluating the performance of the proposed mechanism compared with NEMO basic support protocol and state-of-the-art RO schemes. Numerical and simulation results demonstrate that our proposed mechanism outperforms other RO schemes in terms of handoff latency and total signaling load on wired and wireless links.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.3
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• pp.15-20
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• 2007

Low temperature processed ZnO-TFTs on glass below $270^{\circ}C$ for plastic substrate applications were fabricated and their electrical properties were investigated. Films in ZnO-TFTs with bottom gate configuration were made by RF magnetron sputtering system except for $SiO_2$ gate oxide deposited by ICP-CVD. ZnO channel films were grown on glass with various Ar and $O_2$ flow ratios. All of the fabricated ZnO-TFTs showed perfectly the enhancement mode operation, a high optical transmittance of above 80% in visible ranges of the spectrum. In the ZnO-TFTs with pure Ar process, the field effect mobility, threshold voltage, and on/off ratio were measured to be $1.2\;cm^2/Vs$, 8.5 V, and $5{\times}10^5$, respectively. These characteristic values are much higher than those of the ZnO-TFTs of which ZnO channel layers were processed with additional $O_2$ gas. In addition, ZnO-TFT with pure Af process showed smaller swing voltage of 1.86v/decade compared to those with $Ar+O_2$ process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.7A
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• pp.778-784
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• 2007

Predictive channel reservation techniques have widely been studied in mobile cellular networks in order to meet the desired quality-of-service requirements. Those efforts are mostly concentrated on predicting the target cell that a mobile will move to and reserving the channel before the actual handoff, and subsequently reducing handoff-dropping probability and improving bandwidth utilization. In this paper, we propose adaptive reporting schemes that a mobile reports its mobility status information such as position, speed, and direction in an appropriate moment based on the user's mobility pattern characteristics and, hence the network can make a more-accurate prediction on the user's mobility. We show from the simulations that the proposed scheme is capable of keeping target cell prediction more accurate and required number of reporting through the wireless up-link channel lower.

• The Journal of Korea Robotics Society
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• v.5 no.4
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• pp.339-348
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• 2010

One of the requirements for autonomous vehicles on off-road is to move stably in unstructured environments. Such capacity of autonomous vehicles is one of the most important abilities in consideration of mobility. So, many researchers use contact and/or non-contact methods to determine a terrain whether the vehicle can move on or not. In this paper we introduce an algorithm to classify terrains using visual information(one of the non-contacting methods). As a pre-processing, a contrast enhancement technique is introduced to improve classification of terrain. Also, for conducting classification algorithm, training images are grouped according to materials of the surface, and then Bayesian classification are applied to new images to determine membership to each group. In addition to the classification, we can build Traversability map specified by friction coefficients on which autonomous vehicles can decide to go or not. Experiments are made with Load-Cell to determine real friction coefficients of various terrains.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.7-8
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• 2006

The effects of heat treatment on the electrical properties of SGOI were examined. We proposed the optimized heat treatments for improving the interfacial electrical properties in SGOI-MOSFET. By applying the additional pre-RTA(rapid thermal annealing) before gate oxidation and post-RTA after dopant activation, the driving current, the transconductance, and the leakage current were improved significantly.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1065-1068
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• 2003

For the first time, high quality ultra-thin strained Si/SiGe on Insulator (SGOI) substrate with total SGOI thickness( $T_{Si}$ + $T_{SiGe}$) of 13 nm is developed to combine the device benefits of strained silicon and SOI. In the case of 6- 10 nm-thick top silicon, 100-110 % $I_{d,sat}$ and electron mobility increase are shown in long channel nFET devices. However, 20-30% reduction of $I_{d,sat}$ and electron mobility are observed with 3 nm top silicon for the same long channel device. These results clearly show that the FETs operates with higher performance due to the strain enhancement from the insertion of SiGe layer between the top silicon layer and the buried oxide(BOX) layer. The performance degradation of the extremely thin( 3 nm ) top Si device can be attributed to the scattering of the majority carriers at the interfaces.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.5
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• pp.399-402
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• 2007

The effects of heat treatment on the electrical properties of strained-Si/SiGe-on-insulator (SGOI) devices were examined. We proposed the optimized heat treatment processes for improving the back interfacial electrical properties in SGOI-MOSFET. By applying the additional pre-RTA (rapid thermal annealing) before gate oxidation step and the post-RTA after source/drain dopant activation step, the electrical properties of strained-Si channel on $Si_{1-x}Ge_x$ layer were greatly improved, which resulting the improvement of the driving current, transconductance, and leakage current of SGOI-MOSFET.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.9-18
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• 2005

To make high-performance, low-power transistors beyond the technology node of 60 nm complementary metal-oxide-semiconductor field-effect transistors(C-MOSFETs) possible, the effect of electron mobility of the thickness of strained Si grown on a relaxed SiGe/SiO2/Si was investigated from the viewpoint of mobility enhancement via two approaches. First the parameters for the inter-valley phonon scattering model were optimized. Second, theoretical calculation of the electronic states of the two-fold and four-fold valleys in the strained Si inversion layer were performed, including such characteristics as the energy band diagrams, electron populations, electron concentrations, phonon scattering rate, and phonon-limited electron mobility. The electron mobility in an silicon germanium on insulator(SGOI) n-MOSFET was observed to be about 1.5 to 1.7 times higher than that of a conventional silicon on insulator(SOI) n-MOSFET over the whole range of Si thickness in the SOI structure. This trend was good consistent with our experimental results. In Particular, it was observed that when the strained Si thickness was decreased below 10 nm, the phonon-limited electron mobility in an SGOI n-MOSFT with a Si channel thickness of less than 6 nm differed significantly from that of the conventional SOI n-MOSFET. It can be attributed this difference that some electrons in the strained SGOI n-MOSFET inversion layer tunnelled into the SiGe layer, whereas carrier confinement occurred in the conventional SOI n-MOSFET. In addition, we confirmed that in the Si thickness range of from 10 nm to 3 nm the Phonon-limited electron mobility in an SGOI n-MOSFET was governed by the inter-valley Phonon scattering rate. This result indicates that a fully depleted C-MOSFET with a channel length of less than 15 m should be fabricated on an strained Si SGOI structure in order to obtain a higher drain current.

• Journal of the Korean Vacuum Society
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• v.7 no.s1
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• pp.183-189
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• 1998

A new computer simulation method for film growth, the kinetic Monte Carlo simulation in combination with the results obtained from molecular dynamics simulation for the transient process induced by deposited atoms, was developed. The behavior of energetic atom in Au/Au(100) thin film deposition was investigated by the method. The atomistic mechanism of energetic atom deposition that led to the smoothness enhancement and the relationship between the role of transient process and film growth mechanism were discussed. We found that energetic atoms cannot affect the film growth mode in layer-by-layer at high temperature. However, at temperature of film growth in 3-dimensional mode and in quasi-two-dimensional mode, energetic atoms can enhance the smoothness of film surface. The enhancement of smoothness is caused by the transient mobility of energetic atoms and the suppression for the formation of 3-dimensional islands.

• Journal of Electrical Engineering and Technology
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• v.10 no.3
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• pp.1131-1137
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• 2015

Gallium nitride (GaN) is a promising material for next-generation high-power applications due to its wide bandgap, high breakdown field, high electron mobility, and good thermal conductivity. From a structure point of view, the vertical device is more suitable to high-power applications than planar devices because of its area effectiveness. However, it is challenging to obtain a completely upright vertical structure due to inevitable sidewall slope in anisotropic etching of GaN. In this letter, we design and analyze the enhancement-mode n-channel vertical GaN MOSFET with variation of sidewall gate angle by two-dimensional (2D) technology computer-aided design (TCAD) simulations. As the sidewall slope gets closer to right angle, the device performances are improved since a gradual slope provides a leakage current path through the bulk region.