• Journal of Korea Society of Industrial Information Systems
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• v.13 no.5
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• pp.117-123
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• 2008

In this paper, we develop MPEG-4 AAC streaming player on embedded Linux processor such as mobile terminals. Moreover we show the experimental results that the player preforms the decoding processes of MPEG-4 AAC data effectively. MPEG-4 AAC technology supports a wide range encoding rates and high sound quality so it is appropriate to adopt various applications. In particular, the need in the development of the application of audio data increases according to significantly increase in devices used in mobile environments, such as cell phones and PDAs. In this environment, it is necessary to optimize the decoding processes to the ability of the terminal hardware in order to play audio data without delays. We also implement the decoding module to optimize the processor capabilities and make the player to decode and play streaming audio data from streaming server.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.63-72
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• 2007

In this paper, we propose a novel reconfigurable coprocessor for multimedia mobile terminals. Because most of multimedia operations require fast operations of large amount of data in the limited clock frequency, it is necessary to enhance the performance of the embedded processor that is widely used in current multimedia mobile terminals. Therefore, we proposed and have designed the coprocessor which had the ability of fast operations of multimedia data. The proposed coprocessor was not only reconfigurable, but also flexible and expandable. The proposed coprocessor has been designed by using VHDL and compared with previous reconfigurable coprocessors and a commercial embedded processor in architecture and speed. As a result of the architectural comparison, the proposed coprocessor had better structure in terms of hardware size and flexibility. Also, the simulation results of DCT application showed that the proposed coprocessor was 26 times faster than a commercial ARM processor and 11 times faster than the ARM processor with fast DCT core.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.164-167
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• 2002

This paper presents the design of Rijndael crypto-processor with 128 bits, 192 bits and 256 bits key size. In October 2000 Rijndael cryptographic algorithm is selected as AES(Advanced Encryption Standard) by NIST(National Institute of Standards and Technology). Rijndael algorithm is strong in any known attacks. And it can be efficiently implemented in both hardware and software. We implement Rijndael algorithm in hardware, because hardware implementation gives more fast encryptioN/decryption speed and more physically secure. We implemented Rijndael algorithm for 128 bits, 192 bits and 256 bits key size with VHDL, synthesized with Synopsys, and simulated with ModelSim. This crypto-processor is implemented using on-the-fly key generation method and using lookup table for S-box/SI-box. And the order of Inverse Shift Row operation and Inverse Substitution operation is exchanged in decryption round operation of Rijndael algorithm. It brings about decrease of the total gate count. Crypto-processor implemented in these methods is applied to mobile systems and smart cards, because it has moderate gate count and high speed.

• Journal of the Korea Society of Computer and Information
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• v.4 no.3
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• pp.101-106
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• 1999

Many of study to progress in order to increase of capacity system and multiple access interference to mobile communication environment. In this paper, a proposal to differently processor smart antenna of beamforming technique in spatial processor and rake receiver in the time processor. The performace of DS/CDMA system to multipath fading channel using to beamforming techinque.

• Journal of the Korea Society of Computer and Information
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• v.16 no.5
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• pp.1-11
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• 2011

As the use of mobile multimedia devices is increasing in the recent year, the needs for high-performance multimedia processors are increasing. In this regard, we propose a SIMD (Single Instruction Multiple Data) based parallel processor that supports high-performance multimedia applications with low energy consumption. The proposed parallel processor consists of 16 processing elements (PEs) and operates on a 3-stage pipelining. Experimental results indicated that the proposed parallel processor outperforms conventional parallel processors in terms of performance. In addition, our proposed parallel processor outperforms commercial high-performance TI C6416 DSP in terms of performance (1.4-31.4x better) and energy efficiency (5.9-8.1x better) with same 130nm technology and 720 clock frequency. The proposed parallel processor was developed with verilog HDL and verified with a FPGA prototype system.

• Proceedings of the Korean Information Science Society Conference
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• 2008.06b
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• pp.384-387
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• 2008

PDA와 같은 이동단말에서 화려한 3D 그래픽을 보여주는 것은 그래픽 시스템 리소스의 제약이 있다. Mobile 3D 엔진은 모델의 움직임을 계산하여 동적으로 3D 그래픽을 만들어 내기 때문에 그래픽 시스템 뿐만 아니라, 충분한 성능의 프로세서와 여유의 메모리까지 지원되어야 한다. 본 논문에서는 Mobile 3D 엔진의 제약 사항과 그 해결 방법을 제시하였다. ARM9 Core를 기반으로 3D 가속 기능을 가진 VRender3D에 실제로 OpenGL/ES를 기반으로 하는 Mobile 3D 엔진을 포팅 (porting) 하고, 그 성능을 동적인 3D 영상으로 평가하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.10
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• pp.2605-2619
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• 1996

In this paper, we evaluated performance of mobile exchange control part. Queueing network model is used for modeling of mobile exchange control part. We developed a call control processing and location registration scenartio which has a message exchange function between processors in mobile exchange control part. A network symbol are used the simulation models that are composed of the initialization module, message generation module, message routing module, message processing module, message generation module, HIPC network processing module, output analysis module. as a result of computer simulation, we obtain the processor utilization, the mean queue length, the mean waiting time of control part based on call processing and location registration capacity. The call processing and location registration capacity is referred by thenumber of call attempts in the mobile exchange and must be satisfied with the quality of service(delay time).

• The Journal of Korea Robotics Society
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• v.14 no.4
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• pp.293-300
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• 2019

In this paper, an Embedded solution for fast navigation and precise positioning of mobile robots by floor features is introduced. Most of navigation systems tend to require high-performance computing unit and high quality sensor data. They can produce high accuracy navigation systems but have limited application due to their high cost. The introduced navigation system is designed to be a low cost solution for a wide range of applications such as toys, mobile service robots and education. The key design idea of the system is a simple localization approach using line features of the floor and delayed localization strategy using topological map. It differs from typical navigation approaches which usually use Simultaneous Localization and Mapping (SLAM) technique with high latency localization. This navigation system is implemented on single board Raspberry Pi B+ computer which has 1.4 GHz processor and Redone mobile robot which has maximum speed of 1.1 m/s.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.3
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• pp.490-493
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• 2021

This paper proposes an embedded system that detects mask and face recognition based on a microprocessor instead of Nvidia Jetson Board what is popular development kit. We use a class of efficient models called Mobilenets for mobile and embedded vision applications. MobileNets are based on a streamlined architechture that uses depthwise separable convolutions to build light weight deep neural networks. The device used a Maix development board with CNN hardware acceleration function, and the training model used MobileNet_V2 based SSD(Single Shot Multibox Detector) optimized for mobile devices. To make training model, 7553 face data from Kaggle are used. As a result of test dataset, the AUC (Area Under The Curve) value is as high as 0.98.

• 제어로봇시스템학회:학술대회논문집
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• 1989.10a
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• pp.711-714
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• 1989

Autonomous mobile robot Yamabico and his newly developed ultrasonic range finding module(URF) are described. Yamabico is a self-contained autonomous robot for in-door environment. It has a modularized architecture, which consists of master module, ultrasonic range finding module, locomotion module, voice synthesizer module and console. Newly developed ultrasonic range finding module has a 68000 processor and Dual-port memory for communication. It controls the ultrasonic transmitters and receivers and calculate the range distances for 12-direction, simultaneously within every 60 milliseconds.