• Title/Summary/Keyword: mobile processor

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Implementation of Remote Image Surveillance for Mobile Robot Platform based on Embedded Processor (주행용 로봇 플랫폼을 위한 임베디드 프로세서 기반 원격영상감시 시스템 구현)

  • Han, Kyong-Ho;Yun, Hyo-Won
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.23 no.1
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    • pp.125-131
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    • 2009
  • In this paper, we proposed the remote visual monitoring system on mobile robot platform. The proposed system is composed of ARM9 core PXA255 processor, micro CMOS camera and wireless network and the captured visual image is transmitted via 803.11b/g wireless LAN(WLAN) for remote visual monitoring operations. Robot platform maneuvering command is transmitted via WLAN from host and the $640{\times}480$, $320{\times}240$ pixel fixed visual image is transmitted to host at the rate of $3{\sim}10$ frames per second. Experimental system is implemented on Linux OS base and tested for remote visual monitoring operation and verified the proposed objects.

Analysis of Delay Time in the Personal Communications Exchange (개인통신교환기의 지연시간 분석)

  • Jang, Hee-Seon;Suh, Jae-Jun;Lim, Seog-Ku;Yu, Jea-Hoon;Lee, Yoon-Ju
    • IE interfaces
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    • v.9 no.3
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    • pp.180-193
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    • 1996
  • 본 논문에서는 시뮬레이션 모델을 통해 호유형뿐만 아니라 개인통신서비스에서 필수적인 핸드오버 및 위치등록 등의 모든 트래픽 유형을 고래했을 때 개인통신교환기(PCX : Personal Commuincations Exchange)에서의 지연시간을 분석하며, 지연시간에 대한 결과와 프로세서의 이용율로부터 개인통신교환기의 호처리 및 이동성처리용량을 분석하고 그에 따른 가입자의 수용능력을 추정한다. IPC(Inter-Processor Communications) 메시지의 송수신시간 및 메시지의 처리시간등 교환기 제어계의 성능분석에 필요한 입력 파라미터 값은 기존 ISDN(Integrated Services Digital Network) 및 CMS-MX(CDMA Mobile System-Mobile Exchange) 교환기의 측정자료를 이용하였다. 시뮬레이션 분석결과 PCX 교환기의 호처리 성능은 주로 번호번역 기능을 담당하는 프로세서인 NTP(Number Translation Processor)의 용량에 의해 결정되며, 가입자 밀도가 1,500명$/km^2$인 경우 호처리용량은 약 42만 BHC(Busy Hour Call Completion)로 추정되었고, 이에 상응하는 핸드오버 및 위치등록 처리용량은 각각 시간당 약 2만 6천히 및 40만 6천회로 나타났다. 이것은 가입자당 호처리 부하가 1.6BHC일 경우, 약 15만 7천 가입자를 수용할 수 있는 용량에 해당한다.

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이동통신시스템의 제어국 프로세서를 위한 실시간 사용자 지원 시스템의 설계 및 구현

  • Park, U-Gu;Lee, Je-Heon
    • Journal of KIISE:Computing Practices and Letters
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    • v.6 no.1
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    • pp.93-102
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    • 2000
  • Processors for a base station controller such as call control processor have to serve usersdemand. Some of processors have been still used for the processing of call and 0&M (operation and maintenance) management by adopting embedded board type. This type can not provide users with a wide variety of environments for testing and debugging. User environments are regarded as a primary system factor in most systems and this is particularly so in designing and implementing the processor for base station controller in mobile communication systems. We describe the design and implementation of new user environment tool named QUEST for the next generation mobile communication system, IMT-2000. The simulation results of performance evaluations demonstrate that our system performs well for a base station controller without performance degradation.

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An implementation of Escape and BTA modes for MIPI DSI bridge IC (MIPI DSI 브릿지 IC의 Escape/BTA 모드 구현)

  • Kim, Gyeong-hun;Seo, Chang-sue;Shin, Kyung-wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2014.10a
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    • pp.288-290
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    • 2014
  • In this paper, Escape and BTA(Bus Turn Around) modes of master bridge IC are implemented, which supports MIPI(Mobile Industry Processor Interface) DSI(Display Serial Interface) standard. MIPI DSI master bridge IC sends RGB data and various commands to display module(slave) in order to test it. The Escape mode is designed to implement LPDT, ULPS and trigger message transmissions. The BTA mode is designed to obtain various status information from slave in reverse direction. Functional simulation results show that the designed Escape and BTA modes work correctly for various conditions defined in MIPI DSI standard.

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Mileage-based Asymmetric Multi-core Scheduling for Mobile Devices (모바일 디바이스를 위한 마일리지 기반 비대칭 멀티코어 스케줄링)

  • Lee, Se Won;Lee, Byoung-Hoon;Lim, Sung-Hwa
    • Journal of Korea Society of Industrial Information Systems
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    • v.26 no.5
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    • pp.11-19
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    • 2021
  • In this paper, we proposed an asymmetric multi-core processor scheduling scheme which is based on the mileage of each core. We considered a big-LITTLE multi-core processor structure, which consists of low power consuming LITTLE cores with general performance and high power consuming big cores with high performance. If a task needs to be processed, the processor decides a core type (big or LITTLE) to handle the task, and then investigate the core with the shortest mileage among unoccupied cores. Then assigns the task to the core. We developed a mileage-based balancing algorithm for asymmetric multi-core assignment and showed that the proposed scheduling scheme is more cost-effective compared to the traditional scheme from a management perspective. Simulation is also conducted for the purpose of performance evaluation of our proposed algorithm.

The navigation method of mobile robot using a omni-directional position detection system (전방향 위치검출 시스템을 이용한 이동로봇의 주행방법)

  • Ryu, Ji-Hyoung;Kim, Jee-Hong;Lee, Chang-Goo
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.10 no.2
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    • pp.237-242
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    • 2009
  • Comparing with fixed-type Robots, Mobile Robots have the advantage of extending their workspaces. But this advantage need some sensors to detect mobile robot's position and find their goal point. This article describe the navigation teaching method of mobile robot using omni-directional position detection system. This system offers the brief position data to a processor with simple devices. In other words, when user points a goal point, this system revise the error by comparing its heading angle and position with the goal. For these processes, this system use a conic mirror and a single camera. As a result, this system reduce the image processing time to search the target for mobile robot navigation ordered by user.

Area Efficient Implementation of 32-bit Architecture of ARIA Block Cipher Using Light Weight Diffusion Layer (경량화된 확산계층을 이용한 32-비트 구조의 소형 ARIA 연산기 구현)

  • Ryu, Gwon-Ho;Koo, Bon-Seok;Yang, Sang-Woon;Chang, Tae-Joo
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.16 no.6
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    • pp.15-24
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    • 2006
  • Recently, the importance of the area efficient implementation of cryptographic algorithm for the portable device is increasing. Previous ARIA(Academy, Research Institute, Agency) implementation styles that usually concentrate upon speed, we not suitable for mobile devices in area and power aspects. Thus in this paper, we present an area efficient AR processor which use 32-bit architecture. Using new implementation technique of diffusion layer, the proposed processor has 11301 gates chip area. For 128-bit master key, the ARIA processor needs 87 clock cycles to generate initial round keys, n8 clock cycles to encrypt, and 256 clock cycles to decrypt a 128-bit block of data. Also the processor supports 192-bit and 256-bit master keys. These performances are 7% in area and 13% in speed improved results from previous cases.

Design of Stand-alone AI Processor for Embedded System (독립운용이 가능한 임베디드 인공지능 프로세서 설계)

  • Cho, Kwon Neung;Choi, Do Young;Jeong, Young Woo;Lee, Seung Eun
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2021.05a
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    • pp.600-602
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    • 2021
  • With the development of the mobile industry and growing interest in artificial intelligence (AI) technology, a lot of research for AI processors which applicable to embedded systems is under study. When implementing AI to embedded systems, the design should be considered the restriction of resource and power consumption. Moreover, it is efficient to include a dedicated hardware accelerator in order to complement the low computational performance of the embedded system. In this paper, we propose an stand-alone embedded AI processor. The proposed AI processor includes a hardware accelerator that is dedicated to the distance-based AI algorithm and a general-purpose MCU that supports flexible programmability for application to various embedded systems. The AI processor was designed with Verilog HDL and verified by implementing on Field Programmable Gate Array (FPGA).

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An Implementation of User Interface Simulator dedicated to a Mobile Terminal (이동 단말기용 사용자 인터페이스 시뮬레이터 구현)

  • 이효상;허혜선;홍윤식
    • Proceedings of the IEEK Conference
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    • 1999.06a
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    • pp.1049-1052
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    • 1999
  • We present a use. interface(UI) simulator for developing a mobile phone. This simulator consists of 3 major modules: Graphic Tool Editor, User Interface Software(UI), and Network Command Processor(NCP). The Graphic Tool Editor can design a virtual mobile terminal. The NCP sends a command to the phone and then receives its status from the phone after completion of the command. We can add or modify lots of features easily to the phone using the UI module. These modules can interact each other by sharing the common area in the memory. By doing so, these modules can exchange their status and data to operate in real-time. We have designed and tested a virtual prototyping phone for the LGP 3200 manufactured by LGIC by using the simulator. Through a series of experiment, we have believed that our virtual prototyping interactive simulator can do shorten its development and testing cycle by applying it in the early design phase.

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Maze Navigation System Using Image Recognition for Autonomous Mobile Robot (자율이동로봇의 영상인식 미로탐색시스템)

  • Lee Jeong Hun;Kang Seong-Ho;Eom Ki Hwan
    • Journal of Institute of Control, Robotics and Systems
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    • v.11 no.5
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    • pp.429-434
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    • 2005
  • In this paper, the maze navigation system using image recognition for autonomous mobile robot is proposed. The proposed maze navigation system searches the target by image recognition method based on ADALINE neural network. The infrared sensor system must travel all blocks to find target because it can recognize only one block information each time. But the proposed maze navigation system can reduce the number of traveling blocks because of the ability of sensing several blocks at once. Especially, due to the simplicity of the algorithm, the proposed method could be easily implemented to the system which has low capacity processor.