• 한국전기전자재료학회논문지
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• 제14권3호
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• pp.175-184
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• 2001

In this study, the improved throughput and stability in device fabrication could be obtained by applying CMP process to STi structue in 0.18 um semiconductor device. To employ the CMP process in STI structure, the Reverse Moat Process used to be added after STI Fill, as a result, the process became more complex and the defect were seriously increased than they had been,. Removal rate of each thin film in STI CMP was not uniform, so, the device must have been affected. That is, in case of excessive CMP, the damage on the active area was occurred, and in the case of insufficient CMP nitride remaining was happened on that area. Both of them deteriorated device characteristics. As a solution to these problems, the development of slurry having high removal rate and high oxide to nitride selectivity has been studied. The process using this slurry afford low defect levels, improved yield, and a simplified process flow. In this study, we evaluated the 'High Selectivity Slurry' to do a global planarization without reverse moat step, and also we evaluated EPD(Eend Point Detection) system with which 'in-situ end point detection' is possible.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.90-93
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• 2000

In this study, the rise throughput and the stability in fabrication of device can be obtained by applying of CMP process to STI structure in 0.18um semiconductor device. To employ in STI CMP, the reverse moat process has been added thus the process became complex and the defects were seriously increased. Removal rates of each thin films in STI CMP was not equal hence the devices must to be effected, that is, the damage was occured in the device dimension in the case of excessive CMP process and the nitride film was remained on the device dimension in the case of insufficient CMP process than these defects affect the device characteristics. To resolve these problems, the development of slurry for CMP with high removal rate and high selectivity between each thin films was studied then it can be prevent the reasons of many defects by reasons of many defects by simplification of process that directly apply CMP process to STI structure without the reverse moat pattern process.

• 헤리티지:역사와 과학
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• 제39권
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• pp.59-93
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• 2006

경주 월성은 파사니 사금(婆裟尼師今)때 축조된 신라의 왕성으로서 정치적 군사적으로 매우 중요한 역할을 했던 유적이다. 그러한 월성을 에워싸고 있는 월성해자는 전시(戰時)에는 적으로부터 성을 보호하는 방어적 역할과 함께 통일신라시대에 이르러서는 조경의 역할을 담당한 시설물이다. 월성해자 유적의 발굴은 1985년부터 시작되어 현재 까지 이어지고 있으며, 수많은 유물들이 출토되고 있다. 그 중 다량 다종의 수막새들은 신라 초기부터 통일기를 거쳐 그 이후 시기까지 신라시대 막새의 변화 양상을 보여주는 중요한 자료로서 그 가치는 매우 높다 할 수 있다. 기와는 왕궁(王宮), 사찰(寺刹), 산성(山城) 등 국가적인 사업으로 이루어진 건물에서부터 일반적인 기타 건물지까지 가장 널리 사용되었으며, 수량에서도 다른 유물들에 비해 절대적인 우위를 차지하고 있다. 그럼에도 지금까지의 연구 성과는 가장 취약한 분야로 남아있으며, 앞으로 연구되어야 할 과제들이 무궁하게 남아있는 분야라 할 수 있다. 최근 수많은 발굴을 통한 기와 수량의 급격한 증가와 함께 활발한 연구가 이루어지고 있으나, 일반적인 문양의 계보와 제작과정 등에 한정되어 진행되어 온 것이 사실이다. 이에 여기서는 월성해자 출토 단판연화문 수막새를 대상으로 동범와에 관한 판별을 하고자한다. 그 동안 유사와(類似瓦), 동형와(同形瓦)등으로만 판단되었던 막새들의 세부적 특징을 비교해 "동범와"임을 정확히 확인하고자 한다. 동범와에 관한 정확한 판단방법, 동범와로 묶인 형식의 시간적 순서 배열과 동범와가 출토되는 위치 등을 파악함으로써 동범와 판별에 대한 중요성을 강조하고자 한다. 그 결과 다종의 수막새에서 하나의 범(范)으로 찍어낸 막새, 즉 동범와를 판별할 수 있었으며 이러한 동범와들은 출토위치에서 다시 하나로 묶이는 공통점이 확인된다. 동범와의 출토위치를 통해 월성해자의 시기적인 변천이 어떻게 이루어 졌는지와 주변유적인 안압지와의 연관성도 살펴볼 수 있다. 현재 와범이 확인되지 않아 역으로 막새들의 세부적 특징을 비교해 동범와를 파악할 수 밖에 없는 실정이 다. 하지만 여기서는 동범와라는 용어사용에 있어 동범요소의 정확한 확인 후에 사용되어져야 함을 강조하고, 월성해자 동범와를 통해 월성해자의 지역별 시기를 알아보았다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제50권9호
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• pp.438-443
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• 2001

In the shallow trench isolation(STI)-chemical mechanical polishing(CMP) process, the key issues are the optimized thickness control, within-wafer-non-uniformity, and the possible defects such as pad oxide damage and nitride residue. The defect like nitride residue and silicon (or pad oxide) damage after STI-CMP process were discussed to accomplish its optimum process condition. To understand its optimum process condition, overall STI related processes including reverse moat etch, trench etch, STI fill and STI-CMP were discussed. Consequently, we could conclude that law trench depth and high CMP thickness can cause nitride residue, and high trench depth and over-polishing can cause silicon damage.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.33-36
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• 2001

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The rise throughput and the stability in the device fabrication can be obtained by applying of CMP process to STI structure in 0.18$\mu\textrm{m}$ m semiconductor device. The reverse moat process has been added to employ in of each thin films in STI-CMP was not equal, hence the devices must to be effected, that is, the damage was occurred in the device area for the case of excessive CMP process and the nitride film was remained on the device area for the case of insufficient CMP process, and than, these defects affect the device characteristics. Also, we studied the High Selectivity Slurry(HSS) to perform global planarization without reverse moat step.

• Earthquakes and Structures
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• 제5권5호
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• pp.499-526
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• 2013

Seismic isolation is an effective method for the protection of buildings and their contents during strong earthquakes. This research work aims to assess the appropriateness of the linear and nonlinear models that can be used in the analysis of typical low-rise base isolated steel buildings, taking into account the inherent nonlinearities of the isolation system as well as the potential nonlinearities of the superstructure in case of strong ground motions. The accuracy of the linearization of the isolator properties according to Eurocode 8 is evaluated comparatively with the corresponding response that can be obtained through the nonlinear hysteretic Bouc-Wen constitutive model. The suitability of the linearized model in the determination of the size of the required seismic gap is assessed, under various earthquake intensities, considering relevant methods that are provided by building codes. Furthermore, the validity of the common assumption of elastic behavior for the superstructure is explored and the alteration of the structural response due to the inelastic deformations of the superstructure as a consequence of potential collision to the restraining moat wall is studied. The usage of a nonlinear model for the isolation system is found to be necessary in order to achieve a sufficiently accurate assessment of the structural response and a reliable estimation of the required width of the provided seismic gap. Moreover, the simulations reveal that the superstructure's inelasticity should be taken into account, especially if the response of the structure under high magnitude earthquakes is investigated. The consideration of the inelasticity of the superstructure is also recommended in studies of structural collision of seismically isolated structures to the surrounding moat wall, since it affects the response.

• Korean Chemical Engineering Research
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• 제53권4호
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• pp.472-477
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• 2015

본 연구에서는 패러데이 모트를 사용한 기존의 피코리터 주입용 미세유체 칩에 은 나노입자를 이용한 전극을 추가하여 전압을 낮추며 효율을 높이는 실험을 수행하였다. 먼저, 복잡한 제조공정에서 탈피하여 은 나노입자 용액을 한 방울 떨어뜨리는 간단한 과정만으로 미세유체 피코리터 주입기 내에 전극을 제조하였다. 본 개념을 통한 은 나노입자 전극과 패러데이 모트가 통합된 미세유체 칩은 은 나노입자 전극을 사용하지 않는 기존 미세유체 칩의 피코리터 주입 시작 전압인 260 V 보다 낮은 전압인 180 V에서 피코리터 주입이 작동되었다. 또한 미세유체 피코리터 주입기는 피코리터 주입 부피를 7.5 pL부터 27.5 pL까지 정밀하게 조절할 수 있음을 주된 장점으로 하고 있다. 본 미세유체 피코리터 주입기는 미세유체 시스템의 새로운 기능을 설계함으로써 각 연구분야를 탐구할 유용한 플랫폼으로 기대되고 있다.

• Earthquakes and Structures
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• 제20권3호
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• pp.295-307
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• 2021

The gap provided between adjacent structures in the metropolitan cities is mostly narrow due to architectural and financial issues. Consequently, structural pounding occurs between adjacent structures during earthquakes. It causes damages, ranging from minor local to more severe ones, especially in the case of seismically isolated buildings, due to their higher displacements. However, due to the increased flexibility of isolated buildings, the problem could become more detrimental to such structures. The effect of the seismic pounding of moat walls on the response of buildings isolated by Triple Friction Pendulum Bearing (TFPB) is investigated in this paper. To this propose, two symmetric three-dimensional models, including single-story and five-story buildings, are modeled in Opensees. Nonlinear Time History Analyses (NTHA) are performed for seismic evaluation. Also, five different sizes with four different sets of friction coefficients are considered for base isolators to cover a whole range of base isolation systems with various geometry configurations and fundamental period. The results are investigated in terms of base shear, buildings' drift, and roof acceleration. Results indicated a profound effect of poundings against moat walls. In situations of potential pounding, in some cases, the influence of impact on seismic responses of multistory buildings was more remarkable.

• 한국시뮬레이션학회논문지
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• 제23권3호
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• pp.27-32
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• 2014

본 논문에서는, 초고집적 CMOS 회로를 위한 얕은 트랜치 격리로 기존의 수직 구조 보다 개선된 성질을 갖는 새로운 구조를 제안하고자 한다. 이를 위해서 제안한 구조는 회자 모양의 얕은 트랜치 격리 구조이다. 특성 분석은 기존 수직 구조와 제안한 구조에 대해서 전자농도 분포, 열전자 스트레스의 산화막 모양, 전위와 전계 플럭스, 열 손상의 유전 전계와 소자에서 전류-전압 특성을 분석 하고자 한다. 물리적 기본 모델들은 TCAD 툴을 이용하며, 집적화 소자들에 있어서 분석 조건은 주위 조건과 전류와 시간의 인가 스트레스 조건이다. 분석 결과, 얕은 트랜치 격리 구조가 소자의 크기가 감소됨에 따라서 수동적인 전기적 기능이었다. 트랜지스터 응용에서 제안한 회자 구조의 얕은 트랜치 격리 구조가 전기적 특성에서 전위차, 전계, 전자농도 분포가 높게 나타났으며, 활성영역에서 스트레스에 의한 산화막의 영향은 감소되었다. 이 결과 데이터를 바탕으로 소자의 전류-전압 특성 결과 분석도 양호한 특성으로 나타났다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STD structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters. we studied the correlation between CMP thickness of STI using high selectivity slurry. DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased. the N-poly foot is deteriorated. and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point,, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by $100\AA$. 3.2 $u\AA$ of IDSN is getting better in base 1 condition. In POE 50% condition. 1.7 $u\AA$ is improved. and 0.7 $u\AA$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.