• 한국산업정보학회논문지
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• 제18권1호
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• pp.25-35
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• 2013

Automatically deriving only individual don't-care minterms that can effectively reduce a Boolean logic expressions are being investigated. Don't-care conditions play an important role in optimizing logic design. The type of unknown don't-care minterms that can always reduce the number of product terms in Boolean expression are referred as single hypothetical don't-care (S-HDC) minterms. This paper describes the Quasi Quine-McCluskey method that systematically derives S-HDC minterms. For the most part, this method is similar to the original Quine-McCluskey method in deriving the prime implicants. However, the Quasi Quine-McCluskey method further derives S-HDC minterms by applying so-called a combinatorial comparison operation. Upon completion of the procedure, the designer can review generated S-HDC minterms to test its appropriateness for a particular application.

• 전자공학회논문지B
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• 제29B권11호
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• pp.56-64
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• 1992

The sum-of-product type MVL (Multiple-valued logic) functions can be directly transformed into the exclusive-sum-of-literal-product(ESOLP) type MVL functions with a substitution of the OR operator with the exclusive-OR(XOR) operator. This paper presents an algorithm that can reduce the number of minterms for the purpose of minimizing the hardware size and the complexity of the circuit in the realization of ESOLP-type MVL functions. In Boolean algebra, the joinable true minterms can form the cube, and if some cubes form a cube-chain with adjacent cubes by the insertion of false cubes(or, false minterms), then the created cube-chain can become a large cube which includes previous cubes. As a result of the cube grouping, the number of minterms can be reduced artificially. Since ESOLP-type MVL functions take the MIN/XOR structure, a XOR circuit and a four-valued MIN/XOR dynamic-CMOS PLA circuit is designed for the realization of the minimized functions, and PSPICE simulation results have been also presented for the validation of the proposed algorithm.

• 전기의세계
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• 제28권6호
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• pp.61-77
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• 1979

This paper is concerned with minimization process of the binary logic function. This paper describes an algorithm called the SIMPLE TABLE METHOD that well suited to minimization a switching function of any number of variables. For the Simple Table construction, a theorem based upon the numerical properties of the logic function is derived from the relationships governing minterms of the given function. Finally the minimal sum of products can be obtained in terms of the Direct Method or the Indirect Method from the table and table characteristics derived from the Simple Table. The properties and table characteristics used in this paper are described. All the minterms of a switching function are manipulated only by decimal numbers, not binary numbers. Some examples are used as a vehicle to guide the readers who are familiar with the Karnaugh map and Quine-McCluskey tabular method to this New method. These examples not only treat how to handle Don't Care miterms but also show the multiple output functions.

• 대한전자공학회논문지
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• 제21권4호
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• pp.43-51
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• 1984

부울함수의 간소화법에서 Quine Mcclustey법은 최소항들의 2진수 표현의 구조를 조사하는 방법을 쓰고 있다. 이 논문에서는 10진수로 표현한 최소항을 가지고 그들간의 큐브관계와 간소화에 따르는 제규칙을 정리로 간추려 표현하고 증명하였으며, 이들을 바탕으로 새로운 알고리즘의 부울함수 간소화법을 제안하였다. 예제를 들어 손작업의 방법을 보였고 아울러 이 과정을 FORTRAN 프로그램으로 작성하였다. 프로그램은 여분항을 포함하여 100개까지의 최소항을 가진 부울함수에 대하여 진성주항을 찾아 인쇄하도록 작성하였는데(배열을 크게 잡으면 그 이상도 가능함), 모든 경우에 손작업과 일치하는 결과를 얻었다.

• 대한전자공학회논문지
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• 제23권3호
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• pp.351-356
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• 1986

This paper proposes a new algorithm for logic minimization to optimize the area of a PLA chip. All minterms are expressed in the form of decimal number, and sets of minterms which are not included in the essestia cube are deleted prior to cube generation, ther by making cube generation easy. Also, for reduction of computation time, the properties of multioutput functions are considered. That is, only the combinations of functions correcsponding to common minterms are minimized. The proposed algorithm is implemented on VAX 11/780 using Pascal and compared with conventional methods.

• 한국컴퓨터정보학회논문지
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• 제17권6호
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• pp.83-92
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• 2012

이 논문에서는 십진수의 매트릭스 방법 (DVM) 을 이용한 새로운 방법으로 불리언 논리를 최소화할 때 최소항을 그룹화 하여 표시하는 방법을 제안하고 있다. DVM 방법은 매트릭스 방법을 이용하여 최소항에 관한 이진수의 차이를 십진수 형태로 변환하는 과정을 거치고, 결합할 수 있는 최소항을 직접 확인할 수 있다. 십진수의 매트릭스 방법은 시각적 접근에 따른 새로운 매트릭스이지만, 경우에 따라 주어진 셀 값을 그룹화 하는데 있어서 도형이 복잡해지기도 하는 문제점이 있다. 이 논문은 이러한 문제점을 해결하기 위한 연구로, 십진수의 매트릭스 방법에 최소항의 다단계 그룹을포함하는 기법을 제안하고 있다. 이 연구에서 제시하는 방법은 최소항의 그룹을 간결한 시각적인 방법으로 표현 하였으므로, 관련된 최소항을 구체적으로 파악하는 수단으로 사용할 수 있다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1991년도 하계학술대회 논문집
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• pp.341-344
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• 1991

Rules in expert system have meaning of assigning never-happen-minterms. Overall logical relations of variables can be achived by making all prime implicants of never-happen-minterms. From prime implicants, two tables, which are necessary in the process of inference, are constructed. There are two inferencing modes. One excutes inference only one variable which the user is interested in, and the other excutes inference all variables simultaneously. Outputs of inference have not only 'true' or 'false' but also 'unknown' which is different from conventional expert system. In this paper, an efficient approach is presented, which can check logical inconsistency in knowledge base and contradiction between input facts and rules. The methods in the paper may be available in the field of diagnosis and alarm processing.

• 전기의세계
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• 제29권10호
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• pp.678-688
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• 1980

This paper is concerned with the computer design of the multiple-output switching functions by using the improved MASK method in order to obtain the paramount prime implicants (prime implicants of the multiple-output switching function) and new algorithm to design the optimal logic network. All the given minterms for each function are considered as minterms of one switching function to simplify the desigh procedures. And then the improved MASK method whose memory requirement and time consuming are much less than any existing known method is applied to identify the paramount prime implicants. In selecting the irredundant paramount prime implicants, new cost criteria are generated. This design technuque is suitable both for solving a problem by hand or programming it on a digital computer.

• 전기의세계
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• 제23권4호
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• pp.53-59
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• 1974

This paper investigates the theoretical properties of a logic element called the multithreshold threshold element, which is a generalization of the single-threshold threshold element. The primary partition os a systematic method of obtaining the multi-threshold realization of a switching function by the index numbers. The concept of comparable vertices of the same index numbers introduced in this paper is very promising for testing the multi-threshold partition by the initial condition to be defined by the minterms of the same index numbers.

• 대한전기학회논문지
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• 제39권12호
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• pp.1288-1295
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• 1990

In this paper, we propose a parallel processing model for the efficient selection of Prime Implicants of Logic Functions. This model consists of simple parallel processing nodes, connections between them, Max Net (a part of Hamming Net) and quasi essential Prime Implicant selection standard in simplified cost form. Through these, this model selects essential Prime Implicants in a certain period of time regardless of the number of given Prime Implicants and minterms and also selects quasi essential Prime Implicants in short time.