Journal of the Korean Institute of Telematics and Electronics (대한전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Heuristic Logic-Minimization Algorithm for Programmable Logic Arrays -PLA Logic-Minimization Program PLAMIN-

PLA의 논리최소화를 위한 휴리스틱 알고리즘 -PLA 논리최소화프로그램 PLAMIN-

  • Lee, Jae Min (Dept. of Electronic Eng., Hanyang Univ.) ;
  • Lim, In Chil (Dept. of Electronic Eng., Hanyang Univ.)
  • 이재민 (한양대학교 전자공학과) ;
  • 임인칠 (한양대학교 전자공학과)
  • Published : 1986.03.01
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Abstract

This paper proposes a new algorithm for logic minimization to optimize the area of a PLA chip. All minterms are expressed in the form of decimal number, and sets of minterms which are not included in the essestia cube are deleted prior to cube generation, ther by making cube generation easy. Also, for reduction of computation time, the properties of multioutput functions are considered. That is, only the combinations of functions correcsponding to common minterms are minimized. The proposed algorithm is implemented on VAX 11/780 using Pascal and compared with conventional methods.

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