• Journal of Korea Society of Industrial Information Systems
• /
• v.18 no.1
• /
• pp.25-35
• /
• 2013

Automatically deriving only individual don't-care minterms that can effectively reduce a Boolean logic expressions are being investigated. Don't-care conditions play an important role in optimizing logic design. The type of unknown don't-care minterms that can always reduce the number of product terms in Boolean expression are referred as single hypothetical don't-care (S-HDC) minterms. This paper describes the Quasi Quine-McCluskey method that systematically derives S-HDC minterms. For the most part, this method is similar to the original Quine-McCluskey method in deriving the prime implicants. However, the Quasi Quine-McCluskey method further derives S-HDC minterms by applying so-called a combinatorial comparison operation. Upon completion of the procedure, the designer can review generated S-HDC minterms to test its appropriateness for a particular application.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.29B no.11
• /
• pp.56-64
• /
• 1992

The sum-of-product type MVL (Multiple-valued logic) functions can be directly transformed into the exclusive-sum-of-literal-product(ESOLP) type MVL functions with a substitution of the OR operator with the exclusive-OR(XOR) operator. This paper presents an algorithm that can reduce the number of minterms for the purpose of minimizing the hardware size and the complexity of the circuit in the realization of ESOLP-type MVL functions. In Boolean algebra, the joinable true minterms can form the cube, and if some cubes form a cube-chain with adjacent cubes by the insertion of false cubes(or, false minterms), then the created cube-chain can become a large cube which includes previous cubes. As a result of the cube grouping, the number of minterms can be reduced artificially. Since ESOLP-type MVL functions take the MIN/XOR structure, a XOR circuit and a four-valued MIN/XOR dynamic-CMOS PLA circuit is designed for the realization of the minimized functions, and PSPICE simulation results have been also presented for the validation of the proposed algorithm.

• 전기의세계
• /
• v.28 no.6
• /
• pp.61-77
• /
• 1979

This paper is concerned with minimization process of the binary logic function. This paper describes an algorithm called the SIMPLE TABLE METHOD that well suited to minimization a switching function of any number of variables. For the Simple Table construction, a theorem based upon the numerical properties of the logic function is derived from the relationships governing minterms of the given function. Finally the minimal sum of products can be obtained in terms of the Direct Method or the Indirect Method from the table and table characteristics derived from the Simple Table. The properties and table characteristics used in this paper are described. All the minterms of a switching function are manipulated only by decimal numbers, not binary numbers. Some examples are used as a vehicle to guide the readers who are familiar with the Karnaugh map and Quine-McCluskey tabular method to this New method. These examples not only treat how to handle Don't Care miterms but also show the multiple output functions.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.21 no.4
• /
• pp.43-51
• /
• 1984

In the case of Quine Mccluskey's methode for Boolean function minimization, we have to examine each bits of binary represented minterms. In this paper, cube relations between misterms that are represented by means of decimal number, and all sorts of rules for Boolean function minimization are described as theorems, and they are verified. And based on these theorems, the new fast algorithm for Boolean function minimization is proposed. An example of manual operation is sholvn, and the process is writed out by a FORTRAN program. In this program, the essential pl.imp implicants of the Boolean function that has 100 each of minterms including redundant minterms, are finked and printed out, (the more minterms can be treated if we take the more larger size of arrays) and the outputs are coincided with the results of manual operation.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.23 no.3
• /
• pp.351-356
• /
• 1986

This paper proposes a new algorithm for logic minimization to optimize the area of a PLA chip. All minterms are expressed in the form of decimal number, and sets of minterms which are not included in the essestia cube are deleted prior to cube generation, ther by making cube generation easy. Also, for reduction of computation time, the properties of multioutput functions are considered. That is, only the combinations of functions correcsponding to common minterms are minimized. The proposed algorithm is implemented on VAX 11/780 using Pascal and compared with conventional methods.

• Journal of the Korea Society of Computer and Information
• /
• v.17 no.6
• /
• pp.83-92
• /
• 2012

This paper suggests an improved method of grouping minterms based on the Decimal-Valued Matrix (DVM) method. The DVM is a novel approach to Boolean logic minimization method which was recently developed by this author. Using the minterm-based matrix layout, the method captures binary number based minterm differences in decimal number form. As a result, combinable minterms can be visually identified. Furthermore, they can be systematically processed in finding a minimized Boolean expression. Although this new matrix based approach is visual-based, the suggested method in symmetric grouping cell values can become rather messy in some cases. To alleviate this problem, the enhanced DVM method that is based on multi-level groupings of combinable minterms is presented in this paper. Overall, since the method described here provides a concise visualization of minterm groupings, it facilitates a user with more options to explore different combinable minterm groups for a given Boolean logic minimization problem.

• Proceedings of the KIEE Conference
• /
• 1991.07a
• /
• pp.341-344
• /
• 1991

Rules in expert system have meaning of assigning never-happen-minterms. Overall logical relations of variables can be achived by making all prime implicants of never-happen-minterms. From prime implicants, two tables, which are necessary in the process of inference, are constructed. There are two inferencing modes. One excutes inference only one variable which the user is interested in, and the other excutes inference all variables simultaneously. Outputs of inference have not only 'true' or 'false' but also 'unknown' which is different from conventional expert system. In this paper, an efficient approach is presented, which can check logical inconsistency in knowledge base and contradiction between input facts and rules. The methods in the paper may be available in the field of diagnosis and alarm processing.

• 전기의세계
• /
• v.29 no.10
• /
• pp.678-688
• /
• 1980

This paper is concerned with the computer design of the multiple-output switching functions by using the improved MASK method in order to obtain the paramount prime implicants (prime implicants of the multiple-output switching function) and new algorithm to design the optimal logic network. All the given minterms for each function are considered as minterms of one switching function to simplify the desigh procedures. And then the improved MASK method whose memory requirement and time consuming are much less than any existing known method is applied to identify the paramount prime implicants. In selecting the irredundant paramount prime implicants, new cost criteria are generated. This design technuque is suitable both for solving a problem by hand or programming it on a digital computer.

• 전기의세계
• /
• v.23 no.4
• /
• pp.53-59
• /
• 1974

This paper investigates the theoretical properties of a logic element called the multithreshold threshold element, which is a generalization of the single-threshold threshold element. The primary partition os a systematic method of obtaining the multi-threshold realization of a switching function by the index numbers. The concept of comparable vertices of the same index numbers introduced in this paper is very promising for testing the multi-threshold partition by the initial condition to be defined by the minterms of the same index numbers.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.39 no.12
• /
• pp.1288-1295
• /
• 1990

In this paper, we propose a parallel processing model for the efficient selection of Prime Implicants of Logic Functions. This model consists of simple parallel processing nodes, connections between them, Max Net (a part of Hamming Net) and quasi essential Prime Implicant selection standard in simplified cost form. Through these, this model selects essential Prime Implicants in a certain period of time regardless of the number of given Prime Implicants and minterms and also selects quasi essential Prime Implicants in short time.