• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.212-215
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• 2002

In this paper, we present an intermediate representation CDFG(Control Data Flow Graph) and an efficient scheduling technique for low power circuit design. The proposed CDFG represents control flow, data dependency and such constraints as resource constraints and timing constraints. In the scheduling technique, the constraints are substituted by subgraphs, and then the number of subgraphs is minimized by using the inclusion and overlap relation efficiently. Also, iterative rescheduling process are performed in a minimum bound estimation, starting with the as soon as possible as scheduling result, so as to reduce the power consumption in low power design. The effectiveness of the proposed algorithm has been proven by the experiment with the benchmark examples.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.252-256
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• 2006

A low-power ECC check bit generator is presented with competent DRAM implementation with minimal speed loss, area overhead and power consumption. The ECC used in the proposed scheme is a variant form of the minimum weight column code. The spatial and temporal correlations of input data are analyzed and the input paths of the check bit generator are ordered for the on-line adaptable power savings up to 24.4% in the benchmarked cases. The chip size overhead is estimated to be under 0.3% for a 80nm 1Gb DRAM implementation.

• Journal of Advanced Information Technology and Convergence
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• v.8 no.2
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• pp.59-67
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• 2018

The minimum power supply voltage of a typical bandgap current reference (BGCR) is limited by operating temperature and input common mode range (ICMR) of a feedback amplifier. A new BGCR using a bandgap voltage generator (BGVG) is proposed to minimize the effect of temperature, supply voltage, and process variation. The BGVG is designed with proportional to absolute temperature (PTAT) characteristic, and a feedback amplifier is designed with weak-inversion transistors for low voltage operation. It is verified with a $0.18-{\mu}m$ CMOS process with five corners for MOS transistors and three corners for BJTs. The proposed circuit is superior to other reported current references under temperature variation from $-40^{\circ}C$ to $120^{\circ}C$ and power supply variation from 1.2 V to 1.8 V. The total power consumption is $126{\mu}W$ under the conditions that the power supply voltage is 1.2 V, the output current is $10{\mu}A$, and the operating temperature is $20^{\circ}C$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.4
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• pp.400-406
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• 2014

In this paper, we propose an approach to minimizing total power consumption by deploying multiple clean-up robots simultaneously in a given area. For this, we propose to use the cooperative game theoretic approaches (i.e., Nash bargaining solution (NBS)) such that the robots can optimally and fairly negotiate the area division based on available resources and characteristics of the area, thereby leading to the minimum total power consumption. We define a utility function that includes power consumptions for characteristics of areas and the robots can agree on a utility pair based on the NBS. Simulation results show that the proposed approach can reduce the total average power consumption by 15-30% compared to a random area division approach.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.2
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• pp.31-37
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• 2001

Digital servo implementation in optical servo chip has been spotlighted since it is easy to integrate with other blocks and it has less sensitive characteristics change in terms of temperature variation and better flexibility to the system variation like pick-up. Therefore, Optical disc players adopted digital servo are increasing in market. However, one drawback of digital signal processor embedded digital servo is power consumption that is one of the most important factors of portable optical disc player system. For that reason, this paper introduces new architecture to reduce power consumption of digital servo by means of reducing DSP load but increasing minimum hardware size. The main idea of reducing power consumption of digital servo greatly is utilizing CDP characteristics as most operations are done and used up most operating steps of DSP at the initial time, but most power consumption is occurred in play mode. Therefore, if operating steps for digital filtering in play mode could be reduced greatly, power consumption of overall system can be reduced greatly. This paper shows an example that low power digital servo architecture whose current is reduced almost 83%, compare to that of digital servo which is not applied by the low power architecture introduced in this paper.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.12
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• pp.100-107
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• 1994

This article describes the hardware design scheme of Hamming MAXNET algorithm which is appropriate for binary pattern classification with minimum HD measurement between stimulus vector and storage vector. Circuit integration is profitable to Hamming MAXNET because the structure of hamming network have a few connection nodes over the similar neuro-algorithms. Designed hardware is the two-layered structure composed of hamming network and MAXNET which enable the characteristics of low power consumption and fast operation with biline volgate sensing scheme. Proposed Hamming MAXNET hardware was designed as quantize-level converter for simulation, resulting in the expected binary pattern convergence property.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.12
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• pp.5904-5927
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• 2019

Many artificial intelligence (AI) techniques have been embedded into various engineering technologies to assist them in achieving different goals. The integration of modern technologies with energy consumption management system and occupant's comfort inside buildings results in the introduction of intelligent building concept. The major aim of this integration is to manage the energy consumption effectively and keeping the occupant satisfied with the internal environment of the building. The last few couple of years have seen many applications of AI techniques for optimizing the energy consumption with maximizing the user comfort in smart buildings but still there is much room for improvement in this area. In this paper, a hybrid of two AI algorithms called firefly algorithm (FA) and genetic algorithm (GA) has been used for user comfort maximization with minimum energy consumption inside smart building. A complete user friendly system with data from various sensors, user, processes, power control system and different actuators is developed in this work for reducing power consumption and increase the user comfort. The inputs of optimization algorithms are illumination, temperature and air quality sensors' data and the user set parameters whereas the outputs of the optimization algorithms are optimized parameters. These optimized parameters are the inputs of different fuzzy controllers which change the status of different actuators according to user satisfaction.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.6
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• pp.2711-2733
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• 2018

Minimizing power consumption in bandwidth limited optical traffic grooming networks is presented as a two-objective optimization problem. Since the main objective is to route a connection, the network throughput is maximized first, and then the minimum power consumption solution is found for this maximized throughput. Both transparent IP over WDM (Tp-IPoWDM) and translucent IP over WDM (Tl-IPoWDM) network may be applied to examine such bi-objective algorithms. Simulations show that the bi-objective algorithms are more energy-efficient than the single objective algorithms where only the throughput is optimized. For a Tp-IPoWDM network, both link based ILP (LB-ILP) and path based ILP (PB-ILP) methods are formulated and solved. Simulation results show that PB-ILP can save more power than LB-ILP because PB-ILP has more path selections when lightpath lengths are limited. For a Tl-IPoWDM network, only PB-ILP is formulated and we show that the Tl-IPoWDM network consumes less energy than the Tp-IPoWDM network, especially under a sparse network topology. For both kinds of networks, it is shown that network energy efficiency can be improved by over-provisioning wavelengths, which gives the network more path choices.

• Journal of IKEEE
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• v.10 no.2 s.19
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• pp.103-108
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• 2006

This paper proposed a low power resource allocation algorithm for the minimum switching activity of operators in high level synthesis. In this paper, the proposed method finds switching activity in circuit each functional unit exchange for binary sequence length and value bit are logic one value. To use the switching activity was found the allocation with minimal power consumption, the proposed method visits all control steps one by one and determines the allocation with minimal power consumption at each control step. As the existing method, the execution time can be fast according to use the number of operator and maximal control step. And it is the reduction effect from 8.5% to 9.3%.

• Journal of IKEEE
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• v.10 no.2 s.19
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• pp.134-140
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• 2006

This paper proposed a low power resource allocation algorithm for the minimum switching activity of operators in high level synthesis. In this paper, the proposed method finds switching activity in circuit each functional unit exchange for binary sequence length and value bit are logic one value. To use the switching activity was found the allocation with minimal power consumption, the proposed method visits all control steps one by one and determines the allocation with minimal power consumption at each control step. As the existing method, the execution time can be fast according to use the number of operator and maximal control step. And it is the reduction effect from 8.5% to 9.3%.