• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.5
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• pp.879-884
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• 2009

A Method for detection of saturation of a current transformer(CT) is proposed. The algorithm is initiated when the end point of a saturation period is detected. This detection is achieved by checking the time interval between the adjacent zero-crossing points of the second derivative of the secondary current. Once the end point of the saturation period is detected, the beginning point of the corresponding saturation period is determined by backward examination of the sum of the secondary current from the end point. The performance of the algorithm was evaluated for a-g faults on a 345 kV 100km overhead transmission line. The Electromagnetic Transient Program(EMTP) was used to generate fault current signals for different fault inception angles and different remanent fluxes. The performance evaluation shows that the proposed algorithm successfully detects the saturation period even in the presence of a remanent flux.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.415-418
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• 2011

This paper describes a circuit-level optimization of DFU(decoding function unit) for LDPC decoder which is used in wireless communication systems such as WiMAX and WLAN. The conventional DFU which is based on min-sum decoding algorithm needs conversions between two's complement values and sign-magnitude values, resulting in complex hardware. In this paper, a new design of DFU that is based on sign-magnitude arithmetic is proposed to achieve a simplified circuit and high-speed operation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2A
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• pp.121-127
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• 2010

In this paper, we propose a computationally efficient scheduling algorithm that can arbitrarily control the throughput-fairness tradeoff in a multiuser wireless communication environment. As a new scheduling criterion, we combine linearly two well-known scheduling criteria such as one of achieving the maximum sum throughput and the other of achieving the maximum fairness, so as to control the relative proportion of the throughput and the fairness according to a control factor. For linear combining two different criteria, their optimization directivenesses and the units should be unified first. To meet these requirements, we choose an instantaneous channel capacity as a scheduling criterion for maximizing the sum throughput and the average serving throughput for maximizing the fairness. Through a unified linear combining of two optimization objectives with the control factor, it can provide various throughput-fairness tradeoffs according to the control factors. For further simplification, we exploit a high signal-to-noise ratio (SNR) approximation of the instantaneous channel capacity. Through computer simulations, we evaluate the throughput and fairness performances of the proposed algorithm according to the control factors, assuming an independent Rayleigh fading multiuser channel. We also evaluate the proposed algorithm employing the high SNR approximation. From simulation results, we could see that the proposed algorithm can control arbitrarily the throughput-fairness performance between the performance of the scheduler aiming to the maximum sum throughput and that of the scheduler aiming to the maximum fairness, finally, we see that the high SNR approximation can give a satisfactory performance in this situation.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.8
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• pp.638-651
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• 2000

When the bandwidth resources in a packet-switched network are shared among sessions by MAX-MIN flow control each session is required to transmit its data into the network subject to the MAX-MIN fair rate which is solely determined by network loadings. This passive behavior of sessions if fact can cause seri-ous QoS(Quality of Service) degradation particularly for real-time multimedia sessions such as video since the rate allocated by the network can mismatch with what is demanded by each session for its QoS. In order to alleviate this problem we extend the concept of MAX-MIN fair bandwidth allocations as follows: Individual bandwidth demands are guaranteed if the network can accommodate them and only the residual network band-width is shared in the MAX-MIN fair sense. On the other hand if sum of the individual bandwidth demands exceeds the network capacity the shortage of the bandwidth is shared by all the sessions by reducing each bandwidth guarantee by the MAX-MIN fair division of the shortage. we present a novel flow control algorithm to achieve this extended MAX-MIN fairness and show that this algorithm can be implemented by the existing ATM ABR service protocol with minor changes. We not only analyze the steady state asymptotic stability and convergence rate of the algorithm by appealing to control theories but also verify its practical performance through simulations in a variety of network scenarios.

• Journal of the Korea Society for Simulation
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• v.23 no.4
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• pp.197-202
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• 2014

In order to operate multiple UAVs for multiple tasks efficiently, we need a task allocation algorithm with minimum cost, i.e.,total moving distance required to accomplish the whole mission. In this paper, we have proposed the MCBAA (Modified Consensus Based Auction Algorithm) which can be suitably applied to the operation of multiple UAVs. The key idea of proposed algorithm is to minimize sum of distance from current location of agents to location of tasks based on the conventional CBAA. Several simulation test performed on three UAV agents with multiple tasks demonstrates the overall efficiency both in time and total distance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.18-26
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n wireless LAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. From fixed-point modeling and Matlab simulations for various bit-widths, decoding performance and optimal hardware parameters such as fixed-point bit-width are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.18-${\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.6
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• pp.1355-1362
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. Our LDPC decoder adopts a block-serial architecture based on min-sum algorithm and layered decoding scheme. A novel way to store check-node values and parity check matrix reduces the sizes of check-node memory and H-ROM. An efficient scheme for check-node memory addressing is used to achieve stall-free read/write operations. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.132-135
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.48-58
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• 2016

This paper presents the high-throughput fully-parallel architecture for GF(64) (160,80) regular (2,4) non-binary LDPC (NB-LDPC) codes decoder based on the extended min sum algorithm. We exploit the NB-LDPC code that features a very low check node and variable node degree to reduce the complexity of decoder. This paper designs the fully-parallel architecture and allows the interleaving check node and variable node to increase the throughput of the decoder. We further improve the throughput by the proposed early sorting to reduce the latency of the check node operation. The proposed decoder has the latency of 37 cycles in the one decoding iteration and achieves a high throughput of 1402Mbps at 625MHz.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.5
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• pp.761-766
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• 2008

This paper describes a compensation algorithm for a measurement voltage transformer (VT) based on the hysteresis characteristics of the core. The error of the VT is caused by the voltages across the primary and secondary windings. The latter depends on the secondary current whilst the former depends on the primary current, i.e. the sum of the exciting current and the secondary current. The proposed algorithm calculates the voltages across the primary and secondary windings and add them to the measured secondary voltage for compensation. To do this, the primary and secondary currents should be estimated. The secondary current is obtained directly from the secondary voltage and used to calculate the voltage across the secondary winding. For the primary current, in this paper, the exciting current is decomposed into the two currents, i.e. the core-loss current and the magnetizing current. The core-loss current is obtained by dividing the primary induced voltage by the core-loss resistance. The magnetizing current is obtained by inserting the flux into the flux-magnetizing current curve. The calculated voltages across the primary and secondary windings are added to the measured secondary current for compensation. The proposed compensation algorithm improves the error of the VT significantly.