• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.11
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• pp.56-64
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• 1992

The sum-of-product type MVL (Multiple-valued logic) functions can be directly transformed into the exclusive-sum-of-literal-product(ESOLP) type MVL functions with a substitution of the OR operator with the exclusive-OR(XOR) operator. This paper presents an algorithm that can reduce the number of minterms for the purpose of minimizing the hardware size and the complexity of the circuit in the realization of ESOLP-type MVL functions. In Boolean algebra, the joinable true minterms can form the cube, and if some cubes form a cube-chain with adjacent cubes by the insertion of false cubes(or, false minterms), then the created cube-chain can become a large cube which includes previous cubes. As a result of the cube grouping, the number of minterms can be reduced artificially. Since ESOLP-type MVL functions take the MIN/XOR structure, a XOR circuit and a four-valued MIN/XOR dynamic-CMOS PLA circuit is designed for the realization of the minimized functions, and PSPICE simulation results have been also presented for the validation of the proposed algorithm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.24-33
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• 2012

This paper describes a multi-mode LDPC decoder which supports 19 block lengths and 6 code rates of Quasi-Cyclic LDPC code for Mobile WiMAX system. To achieve an efficient implementation of 114 operation modes, some design optimizations are considered including block-serial layered decoding scheme, a memory reduction technique based on the min-sum decoding algorithm and a novel method for generating the cyclic shift values of parity check matrix. From fixed-point simulations, decoding performance and optimal hardware parameters are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 380,000 gates and 52,992 bits RAM, and the estimated throughput is about 164 ~ 222 Mbps at 56 MHz@1.8 V.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.405-409
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• 2009

In this paper, the effects of LLR (Log-Likelihood Ratio) approximation on LDPC (Low-Density Parity-Check) decoder performance are analyzed, and optimal design conditions of LDPC decoder are derived. The min-sum LDPC decoding algorithm which is based on an approximation of LLR sum-product algorithm is modeled and simulated by MATLAB, and it is analyzed that the effects of LLR approximation bit-width and maximum iteration cycles on the bit error rate (BER) performance of LDCP decoder. The parity check matrix for IEEE 802.11n standard which has block length of 1,944 bits and code rate of 1/2 is used, and AWGN channel with QPSK modulation is assumed. The simulation results show that optimal BER performance is achieved for 7 iteration cycles and LLR bit-width of (7,5).

• Journal of the Korea Computer Graphics Society
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• v.16 no.2
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• pp.9-17
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• 2010

Minkowski sum of two polyedra is an operation to compute the sum of all pairs of points contained in the polyhedra. It has been a very useful tool to solve many geometric problems arising in the areas of robotics, NC machining, solid modeling, and so on. However, very few algorithms have been proposed to compute Minkowski sum of polyhedra, because computing Minkowski sum boundaries is susceptible to roundoff errors. We propose an algorithm to robustly compute the Minkowski sum boundaries by employing the controlled linear perturbation scheme to prevent numerically ambiguous and degenerate cases from occurring. According to our experiments, our algorithm computes the Minkowski sum boundaries with the precision of $10^{-14}$ by perturbing the vertices of the input polyhedra up to $10^{-10}$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.31-40
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• 2010

This paper describes a LDPC decoder for IEEE 802.11n wireless LAN standard. The designed processor supports parity check matrix for block length of 1,944 and code rate of 1/2 in IEEE 802.11n standard. To reduce hardware complexity, the min-sum algorithm and layered decoding architecture are adopted. A novel memory reduction technique suitable for min-sum algorithm was devised, and our design reduces memory size to 25% of conventional method. The LDPC decoder processor synthesized with a $0.35-{\mu}m$ CMOS cell library has 200,400 gates and memory of 19,400 bits, and the estimated throughput is about 135 Mbps at 80 MHz@2.5v. The designed processor is verified by FPGA implementation and BER evaluation to validate the usefulness as a LDPC decoder.

• Journal of Communications and Networks
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• v.12 no.5
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• pp.449-458
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• 2010

In this paper, we present a distributed resource allocation algorithm for multi-cell uplink systems that increases the weighted sum of the average data rates over the entire network under the average transmit power constraint of each mobile station. For the distributed operation, we arrange each base station (BS) to allocate the resource such that its own utility gets maximized in a noncooperative way. We define the utility such that it incorporates both the weighted sum of the average rates in each cell and the induced interference to other cells, which helps to instigate implicit cooperation among the cells. Since the data rates of different cells are coupled through inter-cell interferences, the resource allocation taken by each BS evolves over iterations. We establish that the resource allocation converges to a unique fixed point under reasonable assumptions. We demonstrate through computer simulations that the proposed algorithm can improve the weighted sum of the average rates substantially without requiring any coordination among the base stations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.4
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• pp.876-884
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• 2014

A hardware design of LDPC decoder which is based on the improved normalized min-sum(INMS) decoding algorithm is described in this paper. The designed LDPC decoder supports 19 block lengths(576~2304) and 6 code rates(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6) of IEEE 802.16e mobile WiMAX standard and 3 block lengths(648, 1296, 1944) and 4 code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. The decoding function unit(DFU) which is a main arithmetic block is implemented using sign-magnitude(SM) arithmetic and INMS decoding algorithm to optimize hardware complexity and decoding performance. The LDPC decoder synthesized using a 0.18-${\mu}m$ CMOS cell library with 100 MHz clock has 284,409 gates and RAM of 62,976 bits, and it is verified by FPGA implementation. The estimated performance depending on code rate and block length is about 82~218 Mbps at 100 MHz@1.8V.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.297-298
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• 2008

A new equalization method for perpendicular magnetic recording channels is proposed. The proposed equalizer incorporates the Gaussian sum approximation into a Kalman filtering framework to mitigate inter-symbol interference in perpendicular magnetic recording systems. The proposed equalizer consists of a bank of linear equalizers using the Kalman filtering algorithm and its output is obtained by combining the outputs of linear equalizers through the Gaussian sum approximation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.1
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• pp.189-195
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• 2008

The OFDMA Physical layer in the WiMAX standard of IEEE 802.16e adopts 114 LDPC codes with various code rates and block sizes as a channel coding scheme to meet varying channel environments and different requirements for transmission performance. In this paper, the performances of the LDPC codes are evaluated according to various code rates and block-lengths throueh simulation studies using min-sum decoding algorithm in AWGN chamois. As the block-length increases and the code rate decreases, the BER performance improves. In the cases with code rates of 2/3 and 3/4, where two different codes ate specified for each code rate, the codes with code rates of 2/3A and 3/4B outperform those of 2/3B and 3/4A, respectively. Through the statistical analyses of the number of decoding iterations the decoding complexity and the word error rates of LDPC codes are estimated. The results can be used to trade-off between the performance and the complexity in designs of LDPC decoders.

• Proceedings of the Korean Statistical Society Conference
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• 2002.11a
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• pp.129-132
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• 2002

네트워크를 설계하거나 평가하는데 있어 중요한 문제 중 하나는 그 네트워크를 구성하는 요소들간의 상대적 중요도(importance)에 관한 문제이다. 이런 중요도를 나타내는 여러 가지 측도들 중 하나인 Joint Reliability Importance(JRI)는 Hong & Lie(1993)에 의해 소개되었으며, 네 가지 파생된 서브그래프의 신뢰성을 구하여 JRI를 계산하는 방법이 제시되었다. 본 연구에서는 minimal path set을 이용하여 파생되는 서브 그래프 신뢰성 계산에서의 중복되는 계산과정을 줄임으로써 JRI를 보다 효율적으로 구하는 방법을 제시하고자 한다.