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http://dx.doi.org/10.5573/JSTS.2012.12.1.24

A Multi-mode LDPC Decoder for IEEE 802.16e Mobile WiMAX  

Shin, Kyung-Wook (Kumoh National Institute of Technology - EE)
Kim, Hae-Ju (Silicon Works, Inc.)
Publication Information
Abstract
This paper describes a multi-mode LDPC decoder which supports 19 block lengths and 6 code rates of Quasi-Cyclic LDPC code for Mobile WiMAX system. To achieve an efficient implementation of 114 operation modes, some design optimizations are considered including block-serial layered decoding scheme, a memory reduction technique based on the min-sum decoding algorithm and a novel method for generating the cyclic shift values of parity check matrix. From fixed-point simulations, decoding performance and optimal hardware parameters are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 380,000 gates and 52,992 bits RAM, and the estimated throughput is about 164 ~ 222 Mbps at 56 MHz@1.8 V.
Keywords
Low-density parity-check (LDPC) codes; LDPC decoder; layered decoding; min-sum (MS) algorithm; WiMAX;
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Times Cited By KSCI : 2  (Citation Analysis)
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