• Title/Summary/Keyword: microelectronic package

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The Effect of Manipulating Package Construct and Leadframe Materials on Fracture Potential of Plastically Encapsulated Microelectronic Packages During Thermal Cycling

  • Lee, Seong-Min
    • Transactions on Electrical and Electronic Materials
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    • v.2 no.3
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    • pp.28-32
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    • 2001
  • It was studied in the present work how the thermal cycling performance of LOC (lead on chip) packages depends on the package construct or leadframe materials. First, package body thickness and Au wire diameter were manipulated for the selection of proper package design. Secondly, two different types of leadframe materials (i.e. copper and 52%Fe-48%Ni alloy) were tested to determine the better material for improved reliability margin of plastically encapsulated microelectronic packages. This work shows that manipulating package body thickness was more effective than an increase of Au wire from 23$\mu\textrm{m}$ to 33$\mu\textrm{m}$ for the prevention of wire debonding failure. Further, this work indicates that the LOC packages including the copper leadframes can be more susceptible to thermal cycling reliability degradation due to chip cracking than those including the alloy leadframes.

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Via Filling in Fine Pitched Blind Via Hole of Microelectronic Substrate (마이크로 전자기판의 미세 피치 블라인드 비아홀의 충진 거동)

  • Yi Min-Su;Lee Hyo-S.
    • Journal of the Microelectronics and Packaging Society
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    • v.13 no.1 s.38
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    • pp.43-49
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    • 2006
  • The properties, behavior and reliability of the residual void in blind via hole(BVH) were carried out for the shape of BVH using the void extraction process. The residual void was perfectly removed in the specimens applied by the void extraction process, which was improved by 40% rather than the conventional process. The residual void in BVH was to be eliminated under a condition of 1.5 atm for more 30 sec with regardless of the shape of BVH. It was also observed that the residual void in BVH was not formed after the reliability test with JEDEC standard.

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A Study on Fluxless Soldering using Solder Foil (솔더 포일을 이용한 무플럭스 솔더링에 관한 연구)

  • 신영의;김경섭
    • Journal of Welding and Joining
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    • v.16 no.5
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    • pp.100-107
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    • 1998
  • This paper describes fluxless soldering of reflow soldering process using solder foil instead of solder pastes. There is an increasing demand for the reliable solder connection in the recent high density microelectronic components technologies. And also, it is problem fracture of an Ozone layer due to freon as which is used to removal of remained flux on the substrate. This paper discussed joining phenomena, boudability and joining processes of microelectronics devices, such as between outer lead of VLSI package and copper pad on a substrate without flux. The shear strength of joints is 8 to 13 N using Sn/Pb (63/37 wt.%) solder foil with optimum joining conditions, meanwhile, in case of using Sn/In (52/48 wt.%) solder foil, it is possible to bond with low heating temperature of 550 K, and accomplish to high bonding strength of 25N in condition heating temperature of 650K. Finally, this paper experimentally shows fluxless soldering using solder foil, and accomplishes key technology of microsoldering processes.

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Multilayer thin Film technology as an Enabling technology for System-in-Package (SIP) and "Above-IC" Processing

  • Beyne, Eric
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2003.09a
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    • pp.93-100
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    • 2003
  • The continuing scaling trend in microelectronic circuit technology has a significant impact on the different IC interconnection and packaging technologies. These latter technologies have not kept pace with the IC scaling trends, resulting in a so-called“interconnect technology gap”. Multilayer thin film technology is proposed as a“bridge”- technology between the very high density IC technology and the coarse standard PCB technology. It is also a key enabling technology for the realisation of true“System-in-a-Package”(SIP) solutions, combining multiple“System-on-a-Chip”(SOC) IC's with other components and also integrating passive components in its layers. A further step is to use this technology to realise new functionalities on top of active wafers. These additional“above-IC”processed layers may e.g. be used for low loss, high speed on chip interconnects, clock distribution circuits, efficient power/ground distribution and to realize high Q inductors on chip.

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Thermophysical Properties of PWB for Microelectronic Packages with Solder Resist Coating Process (마이크로 전자패키지용 Printed Wiring Board의 솔더레지스트공정에 따른 열적특성)

  • 이효수
    • Journal of the Microelectronics and Packaging Society
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    • v.10 no.3
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    • pp.73-82
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    • 2003
  • Recently, PWB(Printed Wiring Board) has been recognized in the field of microelectronic package as core technology for designing or manufacturing. PWB is the structure stacked by several materials with different thermophysical properties, which shows the different CTEs(Coefficient or Thermal Expansions) during the fabrication process and causes a lot of defects such as warpage, shrinkage, dimension, etc. Thermal deformation of PWB is affected mainly by the volume change of solder-resist among fabrication parameters. Therefore, thermal deformation of PBGA and CSP consisting of 2 layers and 4 layers was studied with solder-resist process. When over 30% in volume fraction of solder-resist, thermal deformation of 2-layered PWB was min. 40% higher than that of 4-layered PWB because 4-layered PWB contained the layer with high toughness such as prepreg, which counterbalanced the thermal deformation of solder-resist. Otherwise, when below 30%, PWB showed similar thermal deformation without regard to layers and design.

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ALGORITHM OF SEU RATE PREDICTION INSIDE SPACECRAFTS

  • Kim, Y.C.;Lee, J.H.;Shin, Y.H.;Min, K.W.
    • Journal of Astronomy and Space Sciences
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    • v.13 no.1
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    • pp.40-47
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    • 1996
  • One of the important effects of the space environment on the satellites and spacecrafts is the single event upsets (SEUs) which are caused by the high energy particles in space. A SEU occurs when an ionizing radiation produces a burst of electron-hole pairs in a digital microelectronic circuit and causes the charge state to change. We have developed and integrated a software package which can estimate the SEU rates for any specified locations or altitudes under various geophysical conditions. We report in this paper the algorithm of the software and the results for some devices with known parameters. We also compare the results with actual observations made by Akebono.

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Investigation on Hermeticity of Liquid Crystal Polymer Package for MEMS Based Safety Device (MEMS 기반 안전 소자에 대한 액정 폴리머 패키지의 밀폐도 연구)

  • Choi, Jinnil;Kim, Yong-Kook;Ju, Byeong-Kwon
    • Journal of Sensor Science and Technology
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    • v.24 no.5
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    • pp.287-290
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    • 2015
  • Liquid crystal polymer (LCP) is a thermoplastic polymer with superior mechanical and thermal properties. In addition, its characteristics include very low water absorption rate and possibility to apply bonding process under low temperature. In this study, LCP is utilized as a packaging material for a microelectronic system (MEMS) based safety device with suggestion of a low temperature packaging process. Highly sensitive and stable capacitive type humidity sensor is fabricated to investigate hermeticity of the packaged MEMS device.

Highly filled AIN/epoxy composites for microelectronic encapsulation (반도체 봉지용 고충진 AIN/Epoxy 복합재료)

  • 배종우;김원호;황영훈
    • Proceedings of the Korean Society For Composite Materials Conference
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    • 2000.04a
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    • pp.131-134
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    • 2000
  • Increased temperature adversely affects the reliability of a device. So, package material should have high thermal diffusion, i.e., high thermal conductivity. And, there are several other physical properties of polymeric materials that are important to microelectronics packaging, some of which are a low dielectric constant, a low coefficient of thermal expansion (CTE), and a high flexural strength. In this study, to get practical maximum packing fraction of AIN (granular type) filled EMC, the properties such as the spiral flow, thermal conductivity, CTE, and water resistance of AIN-filled EMC (65-vol%) were evaluated according to the size of AIN and the filler-size distribution. Also, physical properties of AIN filled EMC above 65-vol% were evaluated according to increasing AIN content at the point of maximum packing fraction (highly loading condition). The high loading conditions of EMC were set $D_L/D_S$=12 and $X_S$=0.25 like as filler of sphere shape and the AIN filled EMC in this conditions can be obtained satisfactory fluidity up to 70-vol%. As a result, the AIN filled EMC (70-vol%) at high loading condition showed improved thermal conductivity (about 6 W/m-K), dielectric constant (2.0~3.0), CTE(less than 14 ppm/$^{\circ}C$) and water resistance. So, the AIN filled EMC (70-vol%) at high loading condition meets the requirement fur advanced microelectronic packaging materials.

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Thermo-mechanical Behavior of WB-PBGA Packages with Pb-Sn Solder and Lead-free Solder Using Moire Interferometry (무아레 간섭계를 이용한 유연 솔더와 무연 솔더 실장 WB-PBGA 패키지의 열-기계적 변형 거동)

  • Lee, Bong-Hee;Kim, Man-Ki;Joo, Jin-Won
    • Journal of the Microelectronics and Packaging Society
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    • v.17 no.3
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    • pp.17-26
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    • 2010
  • Pb-Sn solder is rapidly being replaced by lead-free solder for board-level interconnection in microelectronic package assemblies due to the environmental protection requirement. There is a general lack of mechanical reliability information available on the lead-free solder. In this study, thermo-mechanical behaviors of wire-bond plastic ball grid array (WB-PBGA) package assemblies are characterized by high-sensitivity moire interferometry. Experiments are conducted for two types of WB-PBGA packages that have Pb-Sn solder and lead-free solder as joint interconnections. Using real-time moire setup, fringe patterns are recorded and analyzed for several temperatures. Bending deformations of the assemblies and average strains of the solder balls are investigated and compared for the two type of WB-PBGA package assemblies. Results show that shear strain in #3 solder ball located near the chip shadow boundary is dominant for the failure of the package with Pb-Sn solder, while normal strain in #7 most outer solder ball is dominant for that with lead-free solder. It is also shown that the package with lead-free solder has much larger bending deformation and 10% larger maximum effective strain than the package with Pb-Sn solder at same temperature level.