• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 추계 기술심포지움
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• pp.55-60
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• 2001

RF MEMS is an exciting emerging technology that has great potential to develop TOC (Transceiver-on-Chip). Applications of the RF MEMS to wireless communications systems are presented. The ability of the RF MEMS technology to enhance the performance and to reduce the size of passive components, in particular, switches, inductors, and tunable capacitors, is addressed. A number of potential wireless system opportunities for the TOC are awaiting the maturation of the RF MEMS technology.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 1999년도 1st Korea-Japan Advanced Semiconductor Packaging Technology Seminar
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• pp.127-154
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• 1999

Interconnect - Wire bonding-> Flip chip interconnect ; At research step, Au stud bump bonding seems to be more proper .Package -Plastic package-> $Z_{0}$ controlled land grid package -Flip Chip will be used for RF ICs and CSP for digital ICs -RF MCM comprised of bare active devices and integrated passive components -Electrical design skills are much more required in RF packaging .Passive Component -discrete-> integrated -Both of size and numbers of passive components must be reduced

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.1137-1140
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• 1999

In this thesis, we research about Communication System Construction and Test-Bed Realization Method and Software’s Design with written program into Embedded Micro Controller’s restricted memory region using a DSP Chip to deal with mainly high speed communication. Tools used for modern communication network control use TI or AMD general chip class, but nevertheless responsibility for the point at issue, Analog Device is architecture design model moderated for small communication system. In this thesis, we present extended model, and realize basic case.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(5)
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• pp.171-174
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• 2000

In stead of RF module which has been used conventionally in many remote measurement applications, a new type of remote measurement system based on PCS(Personal communication system) and one chip Microcontroller is proposed in this work. PCS has many advantages with respect to cost reliability, communication quality, and so on. The proposed system consists of three different modules: PCS module, micro-controller module, and sensor module. System configuration as well as illustrative experiments will be described in detail.

• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 2003년도 춘계학술대회논문집
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• pp.427-733
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• 2003

Adiabatic shear bands have been observed in the serrated chip during high strain rate metal cutting process of medium carbon steel and titanium alloy. The recent microscopic observations have shown that dynamic recrystallization occurs in the narrow adiabatic shear bands. However the conventional flow stress models such as the Zerilli-Armstrong model and the Johnson-Cook model, in general, do not predict the occurrence of dynamic recrystallization (DRX) in the shear bands and the thermal softening effects accompanied by DRX. In the present study, a strain hardening and thermal softening model is proposed to predict the adiabatic shear localized chip formation. The finite element analysis (FEA) with this proposed flow stress model shows that the temperature of the shear band during cutting process rises above 0.5T$\sub$m/. The simulation shows that temperature rises to initiate dynamic recrystallization, dynamic recrystallization lowers the flow stress, and that adiabatic shear localized band and the serrated chip are formed. FEA is also used to predict and compare chip formations of two flow stress models in orthogonal metal cutting with AISI 1045. The predictions of the FEA agreed well with the experimental measurements.

• 한국정밀공학회지
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• 제20권5호
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• pp.218-224
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• 2003

This paper describes a novel MEMS integration technique on a CMOS chip. MEMS integration on CMOS circuit has many advantages in view of manufacturing cost and reliability. The surface topography of a CMOS chip from a commercial foundry has 0.9 ${\mu}{\textrm}{m}$ bumps due to the conformal coating on aluminum interconnect patterns, which are used for addressing each MEMS element individually. Therefore, it is necessary to achieve a flat mirror-like CMOS chip fer the microelectromechanical system (MEMS) such as micro mirror array. Such CMOS chip needs an additional thickness of the dielectric passivation layer to ease the subsequent planarization process. To overcome a temperature limit from the aluminum thermal degradation, this study uses RF sputtering of silicon nitride at low temperature and then polishes the CMOS chip together with the surrounding dummy pieces to define a polishing plane. Planarization reduces 0.9 ${\mu}{\textrm}{m}$ of the bumps to less than 25 nm.

• 한국정보통신학회논문지
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• 제9권6호
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• pp.1282-1287
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• 2005

수 마이크로 단위로 계측되는 반도체 COG의 불량 검사에 있어서 칩 얼라인은 검사의 정확성을 높이는데 매우 중요한 역할을 한다. 본 논문에서는 칩 얼라인의 정확성을 높이기 위해서 영역분할 패턴매칭 방법을 제안한다. 영역분할 패턴매칭 방법은 세분화 된 영역 내의 특징치들과 영역들 간의 상관관계를 비교하여 매칭된다. 그리고 불량 패턴으로 인한 매칭오류를 최소화 하기 위해서 패턴 주위의 3영역을 학습시킨다. 제안된 방법은 분할 된 영역에서 특징치를 찾기 때문에 매칭 시간을 단축시키는 효과와 정확성을 높일 수 있는 이점을 가지고 있다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 추계기술심포지움논문집
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• pp.21-26
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• 2002

Solder flip chip bumping and subsequent coining processes on PCB were investigated to solve the warpage problem of organic substrates for high pin count flip chip assembly by providing good co-planarity. Coining of solder bumps on PCB has been successfully demonstrated using a modified tension/compression tester with height, coining rate and coining temperature variables. It was observed that applied loads as a function of coined height showed three stages as coining deformation : (1) elastic deformation at early stage, (2) linear increase of applied load, and (3) rapid increase of applied load. In order to reduce applied loads for coining solder bumps on PCB, effects of coining process parameters were investigated. Coining loads for solder bump deformation strongly depended on coining rates and coining temperatures. As coining rates decreased and process temperature increased, coining loads decreased. Among the effect of two factors on coining loads, it was found that process temperature had more significant effect to reduce applied coining loads during the coining process. Lower coining loads were needed to prevent substrate damages such as micro-via failure and build-up dielectric layer thickness change during applying loads. For flip chip assembly, 97Pb/Sn flip chip bumped devices were successfully assembled on organic substrates with 37Pb/Sn coined flip chip bumps.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2010년도 춘계학술발표대회 초록집
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• pp.74-74
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• 2010

모바일 정보통신기기를 중심으로 전자패키지의 초소형화, 고집적화를 위해 플립칩 공법의 적용이 증가되고 있는 추세이다. 플립칩 패키징 접합소재로는 솔더, ICA(Isotropic Conductive Adhesive), ACA(Anisotropic Conductive Adhesive), NCA(Non Conductive Adhesive) 등과 같은 다양한 접합소재가 사용되고 있다. 최근에는 언더필을 사용하는 플립칩 공법보다 미세피치 대응성을 위해 NCP를 이용한 플립칩 공법에 대한 요구가 증가되고 있는데, NCP의 상용화를 위해서는 공정성과 함께 신뢰성 확보가 필요하다. 본 연구에서는 LDI(LCD drive IC) 모듈을 위한 COF(Chip-on-Film) 플립칩 패키징용 NCP 포뮬레이션을 개발하고 이를 적용한 COF 패키지의 신뢰성을 조사하였다. 테스트베드는 면적 $1.2{\times}0.9mm$, 두께 $470{\mu}m$, 접속피치 $25{\mu}m$의 Au범프가 형성된 플리칩 실리콘다이와 접속패드가 Sn으로 finish된 폴리이미드 재질의 flexible 기판을 사용하였다. NCP는 에폭시 레진과 산무수물계 경화제, 이미다졸계 촉매제를 사용하여 다양하게 포뮬레이션을 하였다. DSC(Differential Scanning Calorimeter), TGA(Thermogravimetric Analysis), DEA(Dielectric Analysis) 등의 열분석장비를 이용하여 NCP의 물성과 경화거동을 확인하였으며, 본딩 후에는 보이드를 평가하고 Peel 강도를 측정하였다. 최적의 공정으로 제작된 COF 패키지에 대한 HTS (High Temperature Stress), TC (Thermal Cycling), PCT (Pressure Cooker Test)등의 신뢰성 시험을 수행한 결과 양산 적용 가능 수준의 신뢰성을 갖는 것을 확인할 수 있었다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2003년도 춘계학술대회 논문집
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• pp.593-598
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• 2003

Ceramic plates containing many micro-holes are used in diverse applications such as MCP (Microchannel Plate). catalytic converters, filters, electrical insulators in integrated circuits, and so on. One of the efficient methods for machining many holes in ceramic plates is wet drilling of ceramic green bodies followed by sintering them. Since the strength of ceramic green bodies is much lower than the strength of sintered ceramic plate, ceramic green bodies can be drilled with high feed rate. The axial force during micro-drilling of ceramic green bodies increases rapidly at high feed rate, which induces the crack in workpiece. Therefore, the tool lift of micro-drill with respect to feed rate may be determined by the predicting increase of axial force. In this work, the axial force during micro-drilling was calculated using the chip flow model on the micro-drill tip. from which the tool life of diamond abrasive micro-drill during micro-drilling of ceramic green bodies was calculated.