• 한국생산제조학회지
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• 제18권6호
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• pp.636-641
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• 2009

Recently, expansion of micro-technology parts requires micro-precision machining technology. Micro-groove machining is important to fabricate micro-grating lens and many micro-parts such as microscope lens, fluidic graphite channel etc. Conventional groove fabrication methods such as etching and lithography have some problems in efficiency and surface integrity. But, mechanical micromachining methods using single crystal diamond tools can reduce these problems in chemical process. For this reason, microfabrication methods are expected to be very efficient, and widely studied. This study deals with machinability in micro-precision V-grooves machining of nickel plated layer using non-rotational single crystal diamond tool and 3-axis micro stages. Micro V-groove shape, chip formation and tool wear were investigated for the analysis of machinability of Ni plated layer.

• 마이크로전자및패키징학회지
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• 제18권3호
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• pp.59-65
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• 2011

소형화, 박형화 및 집적화의 경향에 따라 FCBGA가 휴대폰과 같은 전자제품에 활발히 사용되고 있다. 그러나, 플립칩은 전기적 저항에 의한 열이 필연적으로 발생하며, 발생된 열은 패키지의 소형화에 따라 열의 분산 면적 감소로 인하여 발열의 증가가 나타나게 된다. 발열은 온도와 응력에 민감하게 반응하는 소자의 수명을 저해하고, 시스템에 있어 고장의 발생을 가져올 수 있다. 따라서 본 논문에서는 플립칩의 발열문제를 해결하기 위하여 Comsol 3.5a의 heat transfer module을 이용하여 FCBGA의 발열 특성을 정량적으로 분석하였다. 그리고 열 문제를 해결하기 위하여 시뮬레이션을 통한 새로운 마이크로 구조가 부착된 플립칩을 제안하였다. 또한 마이크로 패턴 구조의 형상, 높이, 간격에 대한 열 소산을 분석함으로써, 기존 플립칩에 비하여 열소산 특성이 18% 향상됨을 확인하였다.

• 한국ITS학회 논문지
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• 제2권2호
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• pp.65-72
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• 2003

본 연구를 통하여 MMC(Microwave Micro Cell)를 위한 무선 중계 시스템과 ITS용 무선장비등에 사용 될 수있는 6단의 하이브리드 전력증폭기를 설계 및 제작하였다. 전력 증폭기 각단의 능동소자는 bare chip 형태의 Hetero-junction Power FET를 이용하였으며, $\varepsilon_{r}$=9.9, 15-mil 두께의 알루미나기판을 사용하여 제작하였다. 측정 결과 시스템의 순방향 주파수인 17.6GHz - 17.gGEU에서 33.2~36.5dB의 소신호 이득과 33.0$\~$34.0dBm까지의 출력전력을 얻었고, 역방향 주파수인 19.0GHt$\~$19.2GHz에서 36.0$\~$37.0dB의 소신호 이득을 출력전력은 33.0$\~$34.5dBm을 얻었다.

• 전자공학회논문지A
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• 제32A권9호
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• pp.142-151
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• 1995

The trend of compact size, light weight, low power consumption in the portable telecommunication equipments demands large scale integration and low voltage operation of chips and the minimization of the number of the components in the telecommunication terminal. According to the trend, existing chip components are modulized and are integrated as a part into a bigger chip. This paper is about the development of the peripheral units of micro-controller for mobile telecommunication terminal. Peripherals consist of DMA controller, Interrupt controller, timer, watchdog timer, clock generator, and power management unit. They are designed to be integrated with EU(Execution Unit) and BIU(Bus Interface Unit) into a 16 bit micro-controller which will be used as a core of an ASIC for next generation digital mobile telecommunication terminal. At first, whole block of the micro-controller was described by VHDL behavioral model and simulated to verify its overall operation. Then, watchdog timer, clock generator and power management unit were directly synthesized by using VHDL synthesis tool. Rest of the pheriperal units were designed and simulated by using Compass Design Tool.

• 마이크로전자및패키징학회지
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• 제17권4호
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• pp.1-9
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• 2010

삼차원 집적화기술의 현황과 과제 및 향후에 요구되어질 새로운 삼차원 집적화기술의 필요성에 대해 논의를 하였다. Super-chip 기술이라 불리우는 자기조직화 웨이퍼집적화 기술 및 삼차원 헤테로집적화 기술에 대해 소개를 하였다. 액체의 표면장력을 이용하여지지 기반위에 다수의 KGD를 일괄 실장하는 새로운 집적화 기술을 적용하여, KGD만으로 구성된 자기조직화 웨이퍼를 다층으로 적층함으로써 크기가 다른 칩들을 적층하는 것에 성공을 하였다. 또한 삼차원 헤테로집적화 기술을 이용하여 CMOS LSI, MEMS 센서들의 전기소자들과 PD, VC-SEL등의 광학소자 및 micro-fluidic 등의 이종소자들을 삼차원으로 집적하여 시스템화하는데 성공하였다. 이러한 기술은 향후 TSV의 실용화 및 궁극의 3-D IC인 super-chip을 구현하는데 필요한 핵심기술이다.

• 한국산학기술학회논문지
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• 제8권3호
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• pp.454-459
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• 2007

본 논문에서는 비정질 $Al_2O_3$ 코아 재료를 응용한 단순 solenoid 형태의 소형 고성능 RF 칩 인덕터를 연구하였다. 인덕터 크기는 $0.86{\times}0.46{\times}0.45mm^3$이고, $27{\mu}m$ 직경의 Cu를 코일로 사용하였다. RF 칩 인덕터의 인덕턴스(L), 양호 인자(Q), 임피던스(Z), 커패시턴스(C)와 등가회로 파라미터 등의 주파수 특성은 RF impedance/Material Analyzer (HP16193A test fixture가 장착된 HP4291B)로 측정되었다. $9{\sim}12$회의 권선수를 가진 RF 칩 인덕터들의 인덕턴스 값은 $21{\sim}34nH$ 범위를 가진다. 이들의 자기공진주파수(SRF)는 $5.7{\sim}3.7GHz$ 영역을 나타낸다. 또한 자기공진주파수가 증가함에 따라 인덕턴스 값이 감소하는 경향을 보이고 있다. 인덕터의 SRF는 인덕턴스가 증가함에 따라 감소하며, Q의 값은 $900MHz{\sim}1.7GHz$ 주파수 범위에서 최대 $38{\sim}49$까지 얻어졌다.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 2001년도 춘계학술대회 논문집(한국공작기계학회)
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• pp.275-280
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• 2001

Recently, the trends of industrial products grow more miniaturization, variety and mass production. Micro drilling which take high precision in cutting work is requested more micro hole and high speed working. Especially, Micro deep hole drilling is becoming more important in a wide spectrum of precision production industries, ranging from the production of automotive fuel injection nozzle, watch and camera parts, medical needles, and thick multi-layered Printed Circuit Boards(PCB) that are demanded for very high density electric circuitry. This paper shows the tool monitoring results of micro drill with tool dynamometer. And additionally, microscope with built-in monitor inspection show the relationship between burr in workpiece and chip form of micro drill machining.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 1999년도 춘계 기술심포지움 전자부품 및 패키징 기술의 최신동향
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• pp.54-69
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• 1999

• 마이크로전자및패키징학회지
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• 제17권4호
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• pp.73-76
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• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2007년도 춘계학술대회A
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• pp.1673-1678
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• 2007

The use of flip-chip type electronic package offers numerous advantages such as reduced thickness, improved environmental compatibility, and downed cost. Despite numerous benefits, flip-chip type packages bare several reliability problems. The most critical issue among them is their electrical performance deterioration upon consecutive thermal cycles attributed to gradual delamination growth through chip and adhesive film interface induced by CTE mismatch driven shear and peel stresses. The electronic package in use is heated continuously by itself. When the crack at a weak site of the electronic package occurs, thermal deformationon the chip side is changed. Therefore, we can measure these micro deformations by using Moire interferometry and find out the crack length.