• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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• pp.68-69
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• 2011

The process of charge transfer at the interface between two semiconductors or between a metal and a semiconductor plays an important role in many areas of technology. The optimization of such devices requires a good theoretical description of the interfaces involved. This, in turn, has motivated detailed mechanistic studies of interfacial charge-transfer reactions at metal/organic, organic/organic, and organic/inorganic semiconductor heterojunctions. Charge recombination of photo-induced electron with redox species such as oxidized dyes or triiodide or cationic HTM (hole transporting materials) at the heterogeneous interface of $TiO_2$ is one of main loss factors in liquid junction DSSCs or solid-state DSSCs, respectively. Among the attempts to prevent recombination reactions such as insulating thin layer and lithium ions-doped hole transport materials and introduction of co-adsorbents, although co-adsorbents retard the recombination reactions as hydrophobic energy barriers, little attention has been focused on the anchoring processes. Molecular engineering of heterogeneous interfaces by employing several co-adsorbents with different properties altered the surface properties of $TiO_2$ electrodes, resulting to the improved power conversion efficiency and long-term stability of the DSSCs. In this talk, advantages of the coadsorbent-assisted sensitization of N719 in preparation of DSSCs will be discussed.

• 센서학회지
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• 제19권4호
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• pp.328-335
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• 2010

We have designed and fabricated an active pixel sensor(APS) using an optimized n-well/gate-tied p-channel metal oxide semiconductor field effect transistor(PMOSFET)-type photodetector with a built-in transfer gate. This photodetector has a floating gate connected to n-well and a built-in transfer gate. The photodetector has been optimized by changing the length of the transfer gate. The APS has been fabricated using a 0.35 ${\mu}m$ standard complementary metal oxide semiconductor(CMOS) process. It was confirmed that the proposed APS has a wider dynamic range than the APS using the previously proposed photodetector and a higher sensitivity than the conventional APS using a p-n junction photodiode.

• 한국추진공학회:학술대회논문집
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• 한국추진공학회 1994년도 제3회 학술강연회논문집
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• pp.21-26
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• 1994

Conventional electroexplosive devices (EED) commonly use a very small metal bridgewire to ignite explosive materials i.e. pyrotechnics, primary and secondary explosives. The use of semiconductor devices to replace “hot-wire” resistance heating elements in automotive safety systems pyrotechnic devices has been under development for several years. In a typical 1 amp/1 watt electroexplosive devices, ignition takes place a few milliseconds after a current pulse of at least 25 mJ is applied to the bridgewire. In contrast, as for a SCB devices, ignition takes place in a few tens of microseconds and only require approximately one-tenth the input energy of a conventional electroexplosive devices. Typically, when SCB device is driven by a short (20 $\mu\textrm{s}$), low energy pulse (less than 5 mJ), the SCB produces a hot plasma that ignites explosive materials. The advantages and disadvantages of this technology are strongly dependent upon the particular technology selected. To date, three distinct technologies have evolved, each of which utilizes a hot, silicon plasma as the pyrotechnic initiation element. These technologies are 1.) Heavily doped silicon as the resistive heating initiation mechanism, 2.) Tungsten enhanced silicon which utilizes a chemically vapor deposited layer of tungsten as the initiation element, and 3.) a junction diode, fabricated with standard CMOS processes, which creates the initial thermal environment by avalanche breakdown of the diode. This paper describes the three technologies, discusses the advantages and disadvantages of each as they apply to electroexplosive devises, and recommends a methodology for selection of the best device for a particular system environment. The important parameters in this analysis are: All-Fire energy, All-Fire voltage, response time, ease of integration with other semiconductor devices, cost (overall system cost), and reliability. The potential for significant cost savings by integrating several safety functions into the initiator makes this technology worthy of attention by the safety system designer.

• Current Photovoltaic Research
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• 제4권3호
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• pp.108-113
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• 2016

III-V compound semiconductor based thin film solar cells promise relatively higher power conversion efficiencies and better device reliability. In general, the thin film III-V solar cells are fabricated by an epitaxial lift-off process, which requires an $Al_xGa_{1-x}As$ ($x{\geq}0.8$) sacrificial layer and an inverted solar cell structure. However, the device performance of the inversely grown solar cell could be degraded due to the different internal diffusion conditions. In this study, InGaP/GaAs double-junction solar cells are inversely grown by MOCVD on GaAs (100) substrates. The thickness of the GaAs base layer is reduced to minimize the thermal budget during the growth. A wide band gap p-AlGaAs/n-InGaP tunnel junction structure is employed to connect the two subcells with minimal electrical loss. The solar cell structures are transferred on to thin metal films formed by Au electroplating. An AlAs layer with a thickness of 20 nm is used as a sacrificial layer, which is removed by a HF:Acetone (1:1) solution during the epitaxial lift-off process. As a result, the flexible InGaP/GaAs solar cell was fabricated successfully with an efficiency of 27.79% under AM1.5G illumination. The efficiency was kept at almost the same value after bending tests of 1,000 cycles with a radius of curvature of 10 mm.

• Progress in Superconductivity
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• 제8권2호
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• pp.181-185
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• 2007

For more than two decades Nb trilayer ($Nb/Al_2O_3/Nb$) process has been serving as the most stable fabrication process of the Josephson junction integrated circuits. Fast development of semiconductor fabrication technology has been possible with the recent advancement of the fabrication equipments. In this work, we took an advantage of advanced fabrication equipments in developing a superconducting Arithmetic Logic Unit (ALU) by using Nb trilayers. The ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We used DC magnetron sputtering technique for metal depositions and RF sputtering technique for $SiO_2$ depositions. Various dry etching techniques were used to define the Josephson junction areas and film pattering processes. Our Nb films were stress free and showed the $T{_c}'s$ of about 9 K. To enhance the step coverage of Nb films we used reverse bias powered DC magnetron sputtering technique. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. Our 1-bit ALU operated correctly at up to 40 GHz clock frequency, and the 4-bit ALU operated at up to 5 GHz clock frequency.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.408-408
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• 2012

It is well known that magnetic random access memory (MRAM) is nonvolatile memory devices using ferromagnetic materials. MRAM has the merits such as fast access time, unlimited read/write endurance and nonvolatility. Although DRAM has many advantages containing high storage density, fast access time and low power consumption, it becomes volatile when the power is turned off. Owing to the attractive advantages of MRAM, MRAM is being spotlighted as an alternative device in the future. MRAM consists of magnetic tunnel junction (MTJ) stack and complementary metal- oxide semiconductor (CMOS). MTJ stacks are composed of various magnetic materials. FePt thin films are used as a pinned layer of MTJ stack. Up to date, an inductively coupled plasma reactive ion etching (ICPRIE) method of MTJ stacks showed better results in terms of etch rate and etch profile than any other methods such as ion milling, chemical assisted ion etching (CAIE), reactive ion etching (RIE). In order to improve etch profiles without redepositon, a better etching process of MTJ stack needs to be developed by using different etch gases and etch parameters. In this research, influences of $O_2$ gas on the etching characteristics of FePt thin films were investigated. FePt thin films were etched using ICPRIE in $CH_4/O_2/Ar$ gas mix. The etch rate and the etch selectivity were investigated in various $O_2$ concentrations. The etch profiles were studied in varying etch parameters such as coil rf power, dc-bias voltage, and gas pressure. TiN was employed as a hard mask. For observation etch profiles, field emission scanning electron microscopy (FESEM) was used.

• 한국정밀공학회지
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• 제26권11호
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• pp.138-145
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• 2009

A suspended membrane micro fluidic heat flux sensor that is able to measure the heat flow rate was designed and fabricated by a complementary-metal-oxide-semiconductor-compatible process. The combination of a thirty-junction gold and nickel thermoelectric sensor with an ultralow noise preamplifier, low pass filter, and lock-in amp has enabled the resolution of 50 nW power and provides the sensitivity of $11.4\;mV/{\mu}W$. The heater modulation method was used to eliminate low frequency noises from sensor output. It is measured with various heat flux fluid of DI-water to test as micro fluidic application. In order to estimate the heat generation of samples from the output measurement of a micro fluidic heat-flux sensor, a methodology for modeling and simulating electro-thermal behavior in the micro fluidic heat-flux sensor with integrated electronic circuit is presented and validated. The electro-thermal model was constructed by using system dynamics, particularly the bond graph. The electro-thermal system model in which the thermal and the electrical domain are coupled expresses the heat generation of samples converts thermal input to electrical output. The proposed electro-thermal system model shows good agreement with measured output voltage response in transient state and steady-state.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.80-83
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• 2003

In this paper, the programming characteristics of the multi-bit devices based on SONOS structure are investigated. Our devices have been fabricated by $0.35\;{\mu}m$ complementary metal-oxide-semiconductor (CMOS) process with LOCOS isolation. In order to achieve the two-bits per cell operation, charges must be locally trapped in the nitride layer above the channel near the junction. Channel hot electron (CHE) injection for programming can operate in multi-bit using localized trap in nitride film. CHE injection in our devices is achieved with the single power supply of 5 V. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve were investigated. The multi-bit operation which stores two-bit per cell is investigated with a reverse read scheme. Also, hot hole injection for fast erasing is used. Due to the ultra-thin gate dielectrics, our results show many advantages which are simpler process, better scalability and lower programming voltage compared to any other two-bit storage flash memory. This fabricated structure and programming characteristics are shown to be the most promising for the multi-bit flash memory.

• 전력전자학회논문지
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• 제25권5호
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• pp.412-419
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• 2020

In this study, a 70 W buck converter using GaN metal-oxide-semiconductor field-effect transistor (MOSFET) is developed. This converter exhibits over 97 % efficiency, high power density, and 48 V-to-12 V/1.2 V/1 V (triple output). Three gate drivers and six GaN MOSFETs are placed in a 1 ㎠ area to enhance power density and heat dissipation capacity. The theoretical switching and conduction losses of the GaN MOSFETs are calculated. Inductances, capacitances, and resistances for the output filters of the three buck converters are determined to achieve the desired current, voltage ripples, and efficiency. An equivalent circuit model for the thermal analysis of the proposed triple-output buck converter is presented. The junction temperatures of the GaN MOSFETs are estimated using the thermal model. Circuit operation and temperature analysis are evaluated using a circuit simulation tool and the finite element analysis results. An experimental test bed is built to evaluate the proposed design. The estimated switch and heat sink temperatures coincide well with the measured results. The designed buck converter has 130 W/in³ power density and 97.6 % efficiency.

• 한국위성정보통신학회논문지
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• 제7권2호
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• pp.18-24
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• 2012

본 논문에서는 ESD 방지를 위한 최적 방법론에 목표하여 확장된 드레인을 갖는 EDNMOS 소자의 더블 스냅백 현상 및 백그라운 도핑 농도 (BDC)의 영향을 조사하였다. 고전류 영역에서 낮은 BDC를 가진 EDNMOS 소자는 강한 스냅백으로 인해 취약한 ESD 성능과 높은 래치업 위험을 가지게 되나, 높은 BDC를 가진 EDNMOS 소자는 스냅백을 효과적으로 방지할 수 있음을 알 수 있었다. 따라서 BDC 제어로 안정적인 ESD 방지 성능과 래치업 면역을 구현할 수 있음을 밝혔다.