• Korean Journal of Optics and Photonics
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• v.10 no.6
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• pp.518-523
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• 1999

In thi, study, we made experiments to fonn a mesa shape by meltback method with various concentration of solutions and found that unsaturated (20%) InGaAsP (1.55 !-tm) solution at a growth temperature was the most suitable for the formation of a mesa ,hape on the wafer which has an InGaAsP active layer and an InP cap layer on an n-InP substrate. It was difficult to form a proper mesa shape for the fabrication of PBH-LDs only by the meltback method; therefore, we fabricated PBH-LDs by forming the mesa shape with the meltback method after wet etching and by growing a current-blocking layer successively. As the electrical and optical charaleri,tiecs of MQW-PBH-LDs fabricated by above methods, when the cavity length was $300{\mu}m$, the threshold current was about 10 mA, internal quantum efficiency 82%, internal loss $9.2cm^{-1}$, and characteristic temperature was 65 K at $25~45^{\circ}C$ and 42 K at $45~65^{\circ}C$. /TEX>.

• Journal of IKEEE
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• v.13 no.4
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• pp.23-27
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• 2009

Ohmic contact formation and etching processes for the fabrication of MBE (molecular beam epitaxy) grown GaSb-based p-channel HEMT devices on Si substrate have been studied. Firstly, mesa etching process was established for device isolation, based on both HF-based wet etching and ICP-based dry etching. Ohmic contact process for the source and drain formation was also studied based on Ge/Au/Ni/Au metal stack, which resulted in a contact resistance as low as $0.683\;{\Omega}mm$ with RTA at $320^{\circ}C$ for 60s. Finally, for gate formation of HEMT device, gate recess process was studied based on AZ300 developer and citric acid-based wet etching, in which the latter turned out to have high etching selectivity between GaSb and AlGaSb layers that were used as the cap and the barrier of the device, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.25-28
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• 2000

A capacitance-type humidity sensors in which porous silicon layer is used as humidity-sensing material was developed. This sensors was fabricated monolithically to be compatible with the typical IC process technology except for the formation of porous silicon layer. As the sensors is made as a mesa structure, the correct measurement of capacitance is expected because it can remove the effect of the parasitic capacitance from the bottom layer and another junctions. To do this, the sensor was fabricated using process steps such as localized formation of porous silicon, oxidation of porous silicon layer and etching of oxidized porous silicon layer. From completed sensors, capacitance response was measured on the relative humidity of 25 to 95% at room temperature. As the result the measured capacitance showed the increase over 300% at the low frequency of 120Hz, and showed little dependence on the temperature between 10 to $40^{\circ}C$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.824-827
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• 2000

Fabrication of InP-based photonic devices by dry etch Process is important for clear formation of waveguide mesa structure. We have developed more efficient etch process of the inductively coupled plasma (ICP) with low damages and less polymeric deposits for the InP-based photonic devices than the reactive ion etching (RIE) technique. We report the tendency of etch rate variation by the process parameters of the RF power, pressure, gas flow rate, and the gas mixing ratio. The surface roughness of InP-based waveguide structure was more improved by the light wet etching in the mixed solution of H$_2$SO$_4$:H$_2$O (1:1)

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.892-895
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• 2003

This paper describes on RIE(Reactive Ion Etching) characteristics of 3C-SiC(Silicon Carbide) grown on Si(100) wafers. During RIE of 3C-SiC films in this work, $CHF_3$ gas is used to form of polymer as a side wall for excellent anisotropy etching. From this process, etch rates are obtained a $60{\sim}980{\AA}/min$ by various conditions such as $CHF_3$ gas flux, $O_2$ addition ratio, RF power and electrode distance. Also, approximately $40^{\circ}$ mesa structures are successfully formed at 100 mTorr $CHF_3$ gas flow ratio, 200 W RF power and 30 mm electrode distance. Moreover, vertical side wall is fabricated by anisotropy etching with 50% $O_2$ addition ratio and 25 mm electrode distance. Therefore, RIE of 3C-SiC films using $CHF_3$ could be applicable as fabrication process technology for high-temperature 3C-SiC MEMS applications.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.7
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• pp.724-728
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• 2004

This paper describes on RIE(Reactive Ion Etching) characteristics of 3C-SiC(Silicon Carbide) grown on Si(100) wafers. In this work, CHF$_3$ gas was used to form the polymer as a function of a side-wall for excellent anisotropy etching during the RIE process. The ranges of the etch rate were obtained from 60 $\AA$/min to 980 $\AA$/min according to the conditions such as working gas pressure, RF power, distance between electrodes and the $O_2$ addition ratio in working gas pressure. Under the condition such as 100 mTorr of working gas pressure, 200 W of RF power and 30 mm of the distance between electrodes, mesa structures with about 40 of the etch angle were formed, and the vertical structures could be improved with 50 % of $O_2$ addition ratio in reactive gas during the RIE process. As a result of the investigation, we know that it is possible to apply the RIE process of 3C-SiC using CHF$_3$ for the development of electronic parts and MEMS applications in harsh environments.

• Journal of the Korean Vacuum Society
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• v.8 no.4B
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• pp.541-547
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• 1999

Reactive ion etching process for InP using BCl3/O2/Ar high density inductively coupled plasma was investigated. The experimental design method proposed by the Taguchi was utilized to cover the whole parameter range while maintaining reasonable number of actual experiments. Results showed that the ICP power and the chamber pressure were the two dominant parameters affectsing etch results. It was also observed that the etch rate decreased and the surface roughness improved as the ICP power and the bias voltage increased and as the chamber pressure decreased. The Addition of oxygen to the gas mixture drastically improved surface roughness by suppressing the formation of the surface reaction product. The optimum condition was ICP power 600W, bias voltage -100V, 10% $O_2$, 6mTorr, and $180^{\circ}C$, resulting in about 0.15$\mu\textrm{m}$ etch rate with smooth surfaces and vertical mesa sidewalls Also, the maximum etch rate of abut 4.5 $\mu\textrm{m}$/min was obtained at the condition of ICP power 800W, bias voltage -150V, 15% $O_2$, 8mTorr and $160^{\circ}C$.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.10
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• pp.33-40
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• 1993

A reflection type 16x8 S-SEED array from LP(Low Pressure)-MODVD-grown GaAs/AlGaAs extremely shallow quantum well(ESQW) structures, with 4% Al fraction, has been fabricated. Its intrinsic region consists of 50 pairs of alternating 100.angs. GaAs and 100.angs. $Al_{0.04}$Ga$_{0.96}$As layers. A multilayer reflector stack of $Al_{0.04}$/Ga$_{0.96}$ As(599$\AA$)/AlAs(723$\AA$) was incorporated for the reflection plane below the p-i-n structures. The device processing after the MOCVD growth includes the mesa etching, isolation etching, insulator deposition, p & n metallization, and AR(Anti-Reflection) coating. For switching characteristics of the S-SEED in the form of p-i-n ESQW diode, the maximum optical negative resistance was observed at 856nm. Reflectance measurements showed a change from 15.6% to 43.3% for +0.9V to -6V bias. The maximum contrast ration of the S-SEED array was 2.0 and all the 128 devices showed optical bistability with contrast ratios over 2.4 at 5V reverse bias.

• Journal of the Semiconductor & Display Technology
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• v.20 no.3
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• pp.32-38
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• 2021

We developed an inductively coupled plasma (ICP) etcher for GaN etching using a parallel plasma electrode source with a multifunctional chuck matched to it in order for the low power consumption and low process cost in comparison with the conventional ICP system with a helical-type plasma electrode source. The optimization process condition using it for the micro light-emitting diode (µ-LED) chip fabrication was established, which is an ICP RF power of 300 W, a chuck power of 200 W, a BCl₃/Cl₂ gas ratio of 3:2. Under this condition, the mesa structure with the etch depth over 1 ㎛ and the etch angle over 75° and also with no etching residue was obtained for the µ-LED chip. The developed ICP showed the improved values on the process pressure, the etch selectivity, the etch depth uniformity, the etch angle profile and the substrate temperature uniformity in comparison with the commercial ICP. The µ-LED chip fabricated using the developed ICP showed the similar or improved characteristics in the L-I-V measurements compared with the one fabricated using the conventional ICP method

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.10
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• pp.29-34
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• 1992

JFET's with gate lengths ranging from 1$\mu$m to 8.3$\mu$m are successfully fabricated on InP substrate where the long haul (1.3$\mu$m~8.3$\mu$m) OEIC's(OptoElectronic Integrated Circuits) have been made. The pn junction of InP JFET's is made by co-implantation and RTA process. JFET's have etched-mesa-gate structure and the maximum gm larger than 90mS/mm was measured and this is the highest record in JFET's of such structure without S/D n$^{+}$ ion implantation. To maintain maximum g$_m$ should be well controlled the overetch of n-layer which inevitably occurs during etching off the unused p-layer. The I-V characteristic is checked during p-layer etch, for this purpose. A dc voltage gain of 11 is obtained from a preamplifier circuit thus fabricated.