• Proceedings of the Korea Information Processing Society Conference
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• 2012.11a
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• pp.197-199
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• 2012

Recently, a lot of general-purpose application programs in addition to graphic applications have been parallelized for boosting their performance using Graphic Processing Unit (GPU)'s excellent floating-point performance. In order to maximize the application performance on GPUs, optimizing the memory hierarchy and the on-chip caches such as the shared memory is essential. In this paper, we propose techniques to optimize the shared memory, and verify its effectiveness using a pattern matching application program.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 1997.10a
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• pp.35-41
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• 1997

Unit cell analyses were peformed to study the engineering properties of satin weave textile composites. Two 5-harness satin weave layers with fiber tow shifts were modeled by unit cells and repeating boundary conditions were applied at the outer surface of the unit cells. Multi-field macroelements were employed to consider the microstructure details and to effectively reduce computer memory requirements. Preliminary results indicated that the engineering properties of 5-harness satin weave textile composites can vary significantly according to the manner how the adjacent fiber tows were arranged in stacking.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.258-262
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• 2009

In this paper, we propose an effective memory reduction algorithm to reduce the amount of reference frame buffer and memory bandwidth in video encoder and decoder. In general video codecs, decoded previous frames should be stored and referred to reduce temporal redundancy. Recently, reference frames are recompressed for memory efficiency and bandwidth reduction between a main processor and external memory. However, these algorithms could hurt coding efficiency. Several algorithms have been proposed to reduce the amount of reference memory with minimum quality degradation. They still suffer from quality degradation with fixed-bit allocation. In this paper, we propose an adaptive block-based min-max quantization that considers local characteristics of image. In the proposed algorithm, basic process unit is $8{\times}8$ for memory alignment and apply an adaptive quantization to each $4{\times}4$ block for minimizing quality degradation. We found that the proposed algorithm could improve approximately 37.5% in coding efficiency, compared with an existing memory reduction algorithm, at the same memory reduction rate.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.122-130
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• 2013

The demand and the supply are increasing sharply in accordance with the growth of the Memory Semiconductor Industry. The Flash Memory above all is being utilized substantially in the Industry of smart phone, the tablet PC and the System on Chip (SoC). The Flash Memory is divided into the NOR-type Flash Memory and the NAND-type Flash Memory. A lot of study such as the Built-In Self Test (BIST), the Built-In Self Repair (BISR) and the Built-In Redundancy Analysis (BIRA), etc. has been progressed in the NOR-type fash Memory, the study for the Built-In Self Test of the NAND-type Flash Memory has not been progressed. At present, the pattern test of the NAND-type Flash Memory is being carried out using the outside test equipment of high price. The NAND-type Flash Memory is being depended on the outside equipment as there is no Built-In Self Test since the erasure of block unit, the reading and writing of page unit are possible in the NAND-type Flash Memory. The Built-In Self Test equipped with 2 kinds of finite state machine based structure is proposed, so as to carry out the pattern test without the outside pattern test equipment from the NAND-type Flash Memory which carried out the test dependant on the outside pattern test equipment of high price.

• Journal of KIISE:Software and Applications
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• v.37 no.10
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• pp.760-767
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• 2010

There are many memory leak detection tools. However, programmers, who develop very large programs, tend to avoid testing their programs with memory leak detection tools since these tools require runtime and space overheads. Thus, we present a memory leak detection technique which enables programmers to test their modules in their unit test phase with low overheads. To achieve this goal, we extend the existing cyclic memory allocation technique and evaluate our memory leak detection technique on a tiny DBMS. In our experiments, we find our tool has reasonably low runtime and space overheads and it reports only a small number of false positives.

• Proceedings of the Ginseng society Conference
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• 2002.10a
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• pp.20-26
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• 2002

• Journal of the Korean Society for Precision Engineering
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• v.25 no.5
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• pp.82-88
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• 2008

This paper proposes a novel method of 2 dimensional shape display. Shape displays allow us to feel tile actual volume of the object, unlike conventional 2D visual displays of 3D objects. The proposed method employs a wireframe structure to present 2D or 3D objects. The wireframe is composed of small units driven by shape memory alloy (SMA) actuators. The drive unit is analogous to the agonist-antagonist system of animal musculoskeletal systems, where the SMA actuators serve as agonist and antagonist muscles. The force in the SMA actuator is controlled by electrical current. The drive unit is equipped with the locking mechanism so that it can sustain the external force exerted by the user as well as the own weight of the wireframe structure. By controlling the current into the SMA actuator and locking mechanism, we can control the angle of the drive unit. A chain of drive units enables presentation of 2 dimensional objects. 3 dimensional presentations are possible by collecting the chains of drive units.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.55-58
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• 2000

This paper describes a single transistor type ferroelectric field effect transistor (1T FeFET) memory celt scheme which can select one unit memory cell and program/read it. To solve the selection problem of 1T FeEET memory cell array, the row direction common well is electrically isolated from different adjacent row direction column. So, we can control voltage of common well line. By applying bias voltage to Gate and Well, respectively, we can implant IT FeEET memory cell scheme which no interface problem and can bit operation. The results of HSPICE simulations showed the successful operations of the proposed cell scheme.

• Journal of the Semiconductor & Display Technology
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• v.6 no.2 s.19
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• pp.5-10
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• 2007

According to the advantageous features of flash memory, its exploitation and application in mobile and ubiquitous related devices as well as voluminous storage devices is being increased rapidly. The inherent properties that are determined by configuration of flash memory unit might restrict the promising expansion in its utilization. In this paper, we study policies based on threshold values, instead of using global search, in order to satisfy our objective that is to decrease the necessary processing cost or penalty for recycling of flash memory space at the same time minimizing the potential degradation of performance. The proposed cleaning methods create partitions of candidate memory regions, to be reclaimed as free, by utilizing global or dynamic threshold values. The impact of the proposed policies is evaluated through a number of experiments, the composition of the optimal configuration featuring the methods is tested through experiments as well.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.417-422
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• 2010

When memory devices are exposed to space environments, they suffer various effects such as SEU(Single Event Upset). Memory systems for space applications are generally equipped with error detection and correction(EDAC) logics against SEUs. In this paper, several error detection and correction codes - RS(10,8) code, (7,4) Hamming code and (16,8) code - are analyzed and compared with each other. Each code is implemented using VHDL and its performances(encoding/decoding speed, required memory size) are compared. Also the failure probability equation of each EDAC code is derived, and the probability value is analyzed for various occurrence rates of SEUs which the STSAT-3 possibly suffers. Finally, the EDAC algorithm for STSAT-3 is determined based on the comparison results.