• Title/Summary/Keyword: memory testing

Search Result 244, Processing Time 0.025 seconds

Intensity of Aerobic Exercise and Level of Cognitive Task on Computerized Neurobehavioral System

  • Kim, Tae-Hoon;Park, Ji-Hyuk;Kim, Jong-Eon
    • International Journal of Contents
    • /
    • v.6 no.3
    • /
    • pp.83-88
    • /
    • 2010
  • Aerobic exercise affects cerebral circulation, action of neurotransmitters, glucose, oxygen, and energetic substances and influence on the central nervous system for cognition. This study suggests that both the intensity of exercise and the level of cognitive task need to be considered. Computerized neurobehavioral testing is a more effective method, compared to conventional methods, of neuropsychological testing when measuring cognition objectively, in cases that we found. The intensity of 80% max HR had effect on more complex tasks such as 3 Digit Addition and Digit Span Backward, and the intensity of 65% max HR had an effect on more simple tasks such as Color Word Vigilance and Digit Span Forward. We can assume that different intensity of aerobic exercise might involve specific areas of the brain as they could have different sensitivities, so further studies measuring regional cerebral blood flow or electroencephalogram are needed to confirm the results.

The errors and reducing method in the frequency response function from impact hammer testing (충격햄머 가진으로 구한 주파수응답함수의 오차와 해결방법)

  • 안세진;정의봉
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
    • /
    • 2002.05a
    • /
    • pp.71-77
    • /
    • 2002
  • The spectrum of impulse response signal which is obtained from an impulse hammer testing is used for frequency response function, nevertheless it has serious faults when the record length for the signal processing is not very long. The faults cannot be avoided with the conventional signal analyzer that is processing all the signals as if they are always periodic. The signals generated by the impact hammer are undoubtedly non-periodic because of the damping, and are acquired for limited recording time due to the memory as well as the computation performance of the signal analyzer. This paper will make clear the relation between the faults and the length of recording time, and propose the way for solving the faults.

  • PDF

Wireless Impedance Sensor with PZT-Interface for Prestress-Loss Monitoring in Prestressed Concrete Girder

  • Nguyen, Khac-Duy;Lee, So-Young;Kim, Jeong-Tae
    • Journal of the Korean Society for Nondestructive Testing
    • /
    • v.31 no.6
    • /
    • pp.616-625
    • /
    • 2011
  • Ensuring the designed prestress force is very important for the safety of prestressed concrete bridge. The loss of prestress force in tendon could significantly reduce load carrying capacity of the structure. In this study, an automated prestress-loss monitoring system for prestressed concrete girder using PZT-interface and wireless impedance sensor node is presented. The following approaches are carried out to achieve the objective. Firstly, wireless impedance sensor nodes are designed for automated impedance-based monitoring technique. The sensor node is mounted on the high-performance Imote2 sensor platform to fulfill high operating speed, low power requirement and large storage memory. Secondly, a smart PZT-interface designed for monitoring prestress force is described. A linear regression model is established to predict prestress-loss. Finally, a system of the PZT-interface interacted with the wireless sensor node is evaluated from a lab-scale tendon-anchorage connection of a prestressed concrete girder.

Method And Mathematical Algorithm For Finding The Quasi-Optimal Purpose Plan

  • Piskunov, Stanislav;Yuriy, Rayisa;Shabelnyk, Tetiana;Kozyr, Anton;Bashynskyi, Kyrylo;Kovalev, Leonid;Piskunov, Mykola
    • International Journal of Computer Science & Network Security
    • /
    • v.21 no.2
    • /
    • pp.88-92
    • /
    • 2021
  • A method and a mathematical algorithm for finding a quasi-optimal assignment plan with rectangular efficiency matrices are proposed. The developed algorithm can significantly reduce the time and computer memory consumption for its implementation in comparison with optimal methods.

Fractional Integration in the Context of Periodicity: A Monte Carlo Experiment and an Empirical Study

  • Gil-Alana Luis A.
    • Communications for Statistical Applications and Methods
    • /
    • v.13 no.3
    • /
    • pp.587-605
    • /
    • 2006
  • Recent results in applied statistics have shown that the presence of periodicities in time series may influence the estimation and testing of the fractional differencing parameter. In this article, we provide further evidence on the issue by using several procedures of fractional integration. The results show that in the presence of periodicities, the order of integration can be erroneously detected. An empirical application in the context of seasonal data is also carried out at the end of the article.

Area Usage Factor Analyzing Method for Semi-conductor Manufacturing Process

  • Konishi, Katunobu;Ukida, Hiroyuki;Sawada, Koutarou
    • 제어로봇시스템학회:학술대회논문집
    • /
    • 1998.10a
    • /
    • pp.480-483
    • /
    • 1998
  • For memory products, it is very important to develop a new production line as soon as possible. All products are inspected to get rid of defected products at the last testing stage. Those inspection data are called FCM. In this paper, based on the FCM data, Area Usage Factor (AUF) analyzing method will be proposed. Process engineers can make up their mind to which direction they should concentrate their analyzing power.

  • PDF

A new efficient algorithm for test pattern compression considering low power test in SoC (SoC환경에서의 저전력 테스트를 고려한 테스트 패턴 압축에 대한 효율적인 알고리즘)

  • 신용승;강성호
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.41 no.9
    • /
    • pp.85-95
    • /
    • 2004
  • As the design complexity increases, it is a major problem that the size of test pattern is large and power consumption is high in scan, especially system-on-a-chip(SoC), with the automatic test equipment(ATE). Because static compaction of test patterns heads to higher power for testing, it is very hard to reduce the test pattern volume for low power testing. This paper proposes an efficient compression/decompression algorithm based on run-length coding for reducing the amount of test data for low power testing that must be stored on a tester and be transferred to SoC. The experimental results show that the new algorithm is very efficient by reducing the memory space for test patterns and the hardware overhead for the decoder.

An Implementation of Timing Signal Generation Board for 3D Pulse Radar Testing Systems (3차원 펄스 레이다 시험용 타이밍 신호 발생기 구현)

  • Lee, Jong-Pil;Rhee, Ill-Keun;Kim, Hyoun-Ju
    • Journal of IKEEE
    • /
    • v.9 no.2 s.17
    • /
    • pp.136-142
    • /
    • 2005
  • This paper describes some major schemes for developing timing signal generator which can be used for testing of 3D radars. The developed generator has a function not only to simulate information on elevation angle for the simulated target signals but also to generate a modulated signal up to 80MHz. Because this generator has an internal modulating function instead of an external modulating function and has sufficient memory enough to change the parameters according to operating programs, it realization of various test-environments for testing a radar can be made with easy and with low expense.

  • PDF

An Efficient SRAM Testing using Dynamic Power Supply Current (동적 전원 공급 전류를 이용한 효율적인 SRAM 테스트 기법)

  • Yoon, Doe-Hyun;Kim, Hong-Sik;Kang, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.37 no.12
    • /
    • pp.50-59
    • /
    • 2000
  • This paper presents a new SRAM testing method for various faults by monitoring dynamic power supply currents. The peak value of Iddt pulses when the transition write operation is performed, is prominently different from that of a fault free case. Using the observation, a new memory test algorithm is developed which consists of only write operations. The new test algorithm using dynamic power supply current testing, has length of 7n, where n is the number of cells in SRAMs. Compared to the previous March B algorithm, the test length has been reduced by 7/17, and can detect additional hard-to-detect faults.

  • PDF

Automated Coordinator between Testing and Debugging of Embedded Software (임베디드 소프트웨어를 위한 테스트와 디버깅 연계 자동화 방안)

  • Choi, Yoo-Na;Seo, Joo-Young;Choi, Byoung-Ju
    • Journal of KIISE:Computing Practices and Letters
    • /
    • v.16 no.5
    • /
    • pp.576-580
    • /
    • 2010
  • Generally, due to the strong coherence between embedded software and hardware or peripheral software, embedded software is tested by using black-box test based on user scenario for the whole system. This paper suggests the method to coordinate between testing and debugging under consideration for difficulties on solving out the defects detected from black-box test. First of all, from test result analysis, it builds up the debugging strategies enable to trace the locations of the defect's causes. And along with the strategies, it implements the generator of test scripts to be performed on the emulator environment. Through these steps, it can coordinate embedded software testing and debugging activities.