• International Journal of Internet, Broadcasting and Communication
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• v.9 no.1
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• pp.29-34
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• 2017

Over the past several decades, embedded system and flight control computer technologies have been evolved to meet the diverse needs of the mobile device market. Current embedded systems are at the heart of technologies that can take advantage of small-sized specialized hardware while still providing high-efficiency performance at low cost. One of these key technologies is multiple memory banks. For example, a dual memory bank can provide two times more memory bandwidth in the same memory space. This benefit take lower cost to provide the same bandwidth. However, there is still few software technologies to support the efficient use of multiple memory banks. In this study, we present a technique to efficiently exploit multiple memory banks by software support. Specifically, our technique use an interference graph to optimally allocate data to different memory banks by an optimizing compiler. As a result, the execution time can be improved upto 7% with the proposed technique.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.626-633
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• 2006

The wireless sensor networks are sensing, computing and communication infrastructures that allow us to monitor, instrument, observe, and respond to phenomena in the harsh environment. Sensor operating systems that run on tiny sensor nodes are the key to the performance of the distributed computing environment for the wireless sensor networks. Therefore, sensor operating systems should be able to operate efficiently in terms of energy consumption and resource management. In this paper, we present an efficient memory allocation scheme to improve the time and space efficiency of memory management for the sensor operating systems. Our experimental results show that the proposed scheme performs efficiently in both time and space compared with existing memory allocation mechanisms.

• Journal of the Korea Society of Computer and Information
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• v.14 no.3
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• pp.139-147
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• 2009

The memory based reasoning just stores in the memory in the form of the training pattern of the representative pattern. And it classifies through the distance calculation with the test pattern. Because it uses the techniques which stores the training pattern whole in the memory or in which it replaces training patterns with the representative pattern. Due to this, the memory in which it is a lot for the other machine learning techniques is required. And as the moreover stored training pattern increases, the time required for a classification is very much required. In this paper, We propose the EAS(Evaluation And Selection) algorithm in order to minimize memory usage and to improve classification performance. After partitioning the training space, this evaluates each partitioned space as MDL and PM method. The partitioned space in which the evaluation result is most excellent makes into the representative pattern. Remainder partitioned spaces again partitions and repeat the evaluation. We verify the performance of Proposed algorithm using benchmark data sets from UCI Machine Learning Repository.

• Korean Institute of Interior Design Journal
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• v.24 no.4
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• pp.51-60
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• 2015

This study aims to establish the foundation for a simultaneity research, draw the potential through Bergson's simultaneity, and explore a space with the possibility of a continued change, focusing on the simultaneous process, in which physical mobility and consciousness of space last together. First, this study was focused on understanding Bergson's simultaneity, on the basis of the perspective that space needs to have more active, dynamic mobility. For understanding Bergson's simultaneity, the understanding of Bergson's duration conception, memory and perception was preceded. After that, the characteristics of simultaneity were extracted from the concepts of duration, change, memory and perception and its characteristics, which are connected to space, were analyzed. As a result, the study on simultaneity that was intensively analyzed, based on diverse cases, re-awakened the basis of value or thought, which we must aim at, in space design of the present time. This shows the possibility of another creative form that can be found in spaces of the present time and serves as the foundation to discover an essential and potential value of space in space design. Moreover, the combination of space with science, humanities, art and digital media technology demonstrated once again that there is a good possibility of approaching non-representational space that is pursued today and it is anticipated that using Bergson's simultaneity as a medium for spatial combination in their relationship would help in drawing deeper internal meaning and potential of space.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.2
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• pp.75-84
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• 2005

This research is to design a high performance NAND-type flash memory package with a smart buffer cache that enhances the exploitation of spatial and temporal locality. The proposed buffer structure in a NAND flash memory package, called as a smart buffer cache, consists of three parts, i.e., a fully-associative victim buffer with a small block size, a fully-associative spatial buffer with a large block size, and a dynamic fetching unit. This new NAND-type flash memory package can achieve dramatically high performance and low power consumption comparing with any conventional NAND-type flash memory. Our results show that the NAND flash memory package with a smart buffer cache can reduce the miss ratio by around 70% and the average memory access time by around 67%, over the conventional NAND flash memory configuration. Also, the average miss ratio and average memory access time of the package module with smart buffer for a given buffer space (e.g., 3KB) can achieve better performance than package modules with a conventional direct-mapped buffer with eight times(e.g., 32KB) as much space and a fully-associative configuration with twice as much space(e.g., 8KB)

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.136-139
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• 2011

The conventional semiconductor equipment has adopted SRAM module as the test pattern memory, which has a simple design and does not require refreshing. However, SRAM has its disadvantages as it takes up more space as its capacity becomes larger, making it difficult to meet the requirements of large memories and compact size. if DRAM is adopted as the semiconductor inspection equipment, it takes up less space and costs less than SRAM. However, DRAM is also disadvantageous because it requires the memory cell refresh, which is not suitable for the semiconductor examination equipments that require correct timing. Therefore, In this paper, we will proposed an algorithm for punctuality guarantee of memory-free inspection equipment using DDR2 SDRAM. And we will produced memory controller using punctuality guarantee algorithm.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.34 no.1
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• pp.56-64
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• 2006

This paper presents the development and application of a conducting shape memory polyurethane (CSMPU) actuator. While conventional shape memory polyurethanes were activated by external heat source, conducting shape memory polyurethanes introduced in 2004 are activated by electric power. Conducting shape memory polyurethane actuators were manufactured by adding carbon nano tube to conventional shape memory polyurethane. The main problem of the CSMPU developed in 2004 was bad dispersion of carbon nano tubes. In this paper, we tried to find how to solve the dispersion problem, and with a lot of elaborative works, conducting shape memory polyurethane actuators which had better electrical characteristics were developed. Then the actuation performance of the conducting shape memory polyurethane actuators was also measured and assessed. Finally, the possibility of applications were examined through the installation to Micro Air Vehicle.

• The KIPS Transactions:PartA
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• v.11A no.3
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• pp.157-162
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• 2004

This paper suggests the CAMD(Compression Algorithm for in-Memory Data) algorithm that is not moved the pages into the swap space by assigning the compressed cache area in the main memory. The CAMD algorithm that supports the virtual memory system takes high memory usability and performance benefit by reducing the page fault. The memory data is not general data. It is extraordinary data format. In general it consists of specific form of data. Therefore. the CAMD algorithm can compress this data efficiently.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.3
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• pp.151-156
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• 2015

Recently, an embedded flash memory has been widely used for the Internet of Things(IoT). Due to its nonvolatility, economical feasibility, stability, low power usage, and fast speed. With respect to power consumption, the embedded memory system must consider the most significant design factor. The objective of this research is to design high performance and low power NAND flash memory architecture including a dual buffer as a replacement for NOR flash. Simulation shows that the proposed NAND flash system can achieve better performance than a conventional NOR flash memory. Furthermore, the average memory access time of the proposed system is better that of other buffer systems with three times more space. The use of a small buffer results in a significant reduction in power consumption.

• ETRI Journal
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• v.39 no.3
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• pp.428-436
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• 2017

State-of-the-art processors require increasingly complicated memory services for high performance and low power consumption. In particular, they request transfers within a burst in a wrap-around order to minimize the miss penalty of a cache. However, synchronous dynamic random access memories (SDRAMs) do not always generate transfers in the wrap-round order required by the processors. Thus, a memory subsystem rearranges the SDRAM transfers in the wrap-around order, but the rearrangement process may increase memory latency and waste the bandwidth of on-chip interconnects. In this paper, we present a memory subsystem that is effective for the wrapping bursts of a cache. The proposed memory subsystem makes SDRAMs generate transfers in an intermediate order, where the transfers are rearranged in the wrap-around order with minimal penalties. Then, the transfers are delivered with priority, depending on the program locality in space. Experimental results showed that the proposed memory subsystem minimizes the memory performance loss resulting from wrapping bursts and, thus, improves program execution time.