• Proceedings of the KIEE Conference
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• 1998.11b
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• pp.672-674
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• 1998

Java virtual machine has the garbage collector that automate memory management. Mark-compact algorithm is one of the garbage collection algorithm that operating in 2 phases, marking and sweeping. One is Marking is marking live objects reachable from root object set. Sweeping is sweeping unmarked object from memory(return to free memory pool). This algorithm is easy to implement but cause a memory fragmentation. So compacting memory, before memory defragmentation become serious. When compacting memory, all other processes are suspended. It is critical for embedded system that must guarantee real-time processing. This paper introduce enhanced mark-compact garbage collection algorithm. Grouping the objects by their size that minimize memory fragmentation. Then apply smart algorithm to the grouped objects when allocating objects and compacting memory.

• Journal of the Korean Ceramic Society
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• v.16 no.1
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• pp.26-30
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• 1979

The microstructures and memory core characteristics of substituted lithium ferrites with addition of $Bi_2O_3$, $V_2O_5$, $Nb_2O_3$, and $P_2O_5$ were investigated. The effects of composite flux on the sintering of the substituted lithium ferrites were also studied. The results show that the addition of $Bi_2O_3$, $V_2O_5$, and $Nb_2O_5$ enhances sintering whereas $Sb_2O_3$ and $P_2O_5$ inhibits it, and that the addition of $Nb_2O_5$ results in uniform grain size while the addition of $Bi_2O_3$ or $V_2O_5$ results in non-uniformity in grain size. When $P_2O_5$ was added with $V_2O_5$ or $Bi_2O_3$, however, it results in uniform grain size and improved memory core properties.

• 연구논문집
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• s.22
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• pp.127-139
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• 1992

The mechnial properties such as fracture strength, ductility and fatigue strength of Cu shape memory alloy are lower than those of Ti-Ni SMA, because of their high elastic anisotropy and large grain size. And in order to improve the mechanical property of Cu SMA, some techniques such as casting method by addition of refining element, powder metallurgy and rapid solidification process have been studied on the refinement of the grain size of Cu SMA. This study was carried out to refine the grain size of CuAlNi SMA by applying the melt spinning method. According to this study, the conclusions are as follows; - grain size of the melt-spun ribbon was about $1\mum$ - there was not change in grain size, although increasing of hot pressing temperature -grain size of the hot-extruded specimen was about $30-40\mum$, it is more refiner than that of castings

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.237-240
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• 2003

Efficient memory management is one of the most crucial requirement of lava virtual machine. In Java, memory is allocated everytime when a new instance of class is created or when a method is called. The allocated memory is freed when the instance is no longer used, or when the called method is returned. In this paper we have examined the memory management scheme applied to the simpleRTJ lava virtual machine. The simpleRTJ has such a distinguished characteristic in its memory management scheme that the size of all instances are forced to be the same and the size of stack frames of all methods be the same, respectively. We present in this paper the scheme thoroughly and analyze its anticipated performance qualitatively.

• The Transactions of the Korea Information Processing Society
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• v.5 no.1
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• pp.24-32
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• 1998

The bus contention among bus-based shared-memory multiprocessors limits their performance. In addition, under split bus transaction environment, multiprocessors may make some memory requests unnecessary stand by in the memory access buffer, which makes system performance worse. This unnecessary stand-by can be eliminated by maintaining the bitmap table which contains the status bit for each memory block. However, this mechanism requires a great size of SRAM for the status information, which is fully mapped from the whole memory blocks. To solve this problem, we propose a bitmap cache which exploits partial mapping and locality of references. The simulation results show that the proposed system can greatly reduce the capacity of SRAM for the status information with little deteriorating its performance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.15-16
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• 2005

Chalcogenide phase change memory has high performance to be next generation memory, because it is a nonvolatile memory processing high programming speed, low programming voltage, high sensing margin, low consumption and long cycle duration. We have developed a new material of PRAM with $Ge_1Se_1Te_2$. This material has been propose to solve the high energy consumption and high programming current. We have investigated the phase transition behaviors in function of various process factor including contact size, cell size, and annealing time. As a result, we have observed that programming voltage and writing current of $Ge_1Se_1Te_2$ are more improved than $Ge_2Sb_2Te_5$ material.

• Journal of IKEEE
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• v.25 no.3
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• pp.479-484
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• 2021

This paper proposed and designed a structure to achieve high performance with a small number of cores in GPGPU with SIMT structure. GPGPU for application to mobile devices requires a structure to increase performance compared to power consumption. In order to reduce power consumption, the number of cores decreased, but to improve performance, the size of the warp scheduler for managing threads was set to 4, which was greatly reduced than 32 of general GPGPU. Reducing warp size can reduce the number of idle cycles in pipelines and efficiently apply memory latency to reduce miss penalty when accessing cache memory. The designed GPGPU measured computational performance using a test program that includes floating point operations and measured power consumption through a 28nm CMOS process to obtain 104.5GFlops/Watt as a performance per power. The results of this paper showed about four times better performance per power compared to Tegra K1 of Nvidia

• Proceedings of the KIEE Conference
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• 1989.11a
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• pp.488-493
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• 1989

In this paper, the structure of CMAC address mapping is first revisited, and the address hashing function and the random mapping is discussed in the conventional CMAC implementation. Then the effective size of CMAC memory is derived from the modulus property of the CMAC address vector, and a new hashing function for the effective memory mapping is proposed for a CMAC implementation with feasible memory size and no troublesome random mapping. Finally, the performance of the conventional CMAC learning algorithm and that of the proposed new CMAC scheme arc compared via simulations.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.6
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• pp.65-70
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• 2021

Recently, as the number of mobile apps rapidly increases, the memory size of smartphones keeps increasing. Smartphone memory consists of DRAM and as it is a volatile medium, continuous refresh operations for all cells should be performed to maintain the contents. Thus, the power consumption of memory increases in proportion to the DRAM size of the system. There are attempts to configure the memory system with low-power non-volatile memory instead of DRAM to reduce the power consumption of smartphones. However, non-volatile memory has weaknesses in write operations, so analysis of write behaviors is a prerequisite to realize this in practical systems. In this paper, we extract memory reference traces of mobile apps and analyze their characteristics specially focusing on write operations. The results of this paper will be helpful in the design of memory management systems consisting of non-volatile memory in future smartphones.

• Journal of Applied Reliability
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• v.10 no.1
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• pp.65-71
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• 2010

NAND-type SONOS with a separated double-gate FinFET structure (SDF-Fin SONOS) flash memory devices are proposed to reduce the unit cell size of the memory device and increase the memory density in comparison with conventional non volatile memory devices. The proposed memory device consists of a pair of control gates separated along the direction of the Fin width. There are two unique alternative technologies in this study. One is a channel doping method and the other is an oxide thickness variation method, which are used to operate the SDF-Fin SONOS memory device as two-bit. The fabrication processes and the device characteristics are simulated by using technology comuter-adided(TCAD). The simulation results indicate that the charge trap probability depends on the different channel doping concentration and the tunneling oxide thickness. The proposed SDG-Fin SONOS memory devices hold promise for potential application.