• Journal of KIISE:Computer Systems and Theory
• /
• v.32 no.4
• /
• pp.177-185
• /
• 2005

NAND-type flash memory is becoming increasingly popular as a large data storage for mobile computing devices. Since flash memory is an order of magnitude more expensive than magnetic disks, data compression can be effectively used in managing flash memory based storage systems. However, compressed data management in NAND-type flash memory is challenging because it supports only page-based I/Os. For example, when the size of compressed data is smaller than the page size. internal fragmentation occurs and this degrades the effectiveness of compression seriously. In this paper, we present an efficient flash compression layer (FCL) for NAND-type flash memory which stores several small compressed pages into one physical page by using a write buffer Based on prototype implementation and simulation studies, we show that the proposed scheme offers the storage of flash memory more than $140\%$ of its original size and expands the write bandwidth significantly.

• Journal of the Semiconductor & Display Technology
• /
• v.21 no.4
• /
• pp.45-49
• /
• 2022

Through Silicon Via (TSV) is a technology that interconnects chips through silicon vias. TSV technology can achieve shorter distance compared to wire bonding technology with excellent electrical characteristics. Due to this characteristic, it is currently being used in many fields that needs faster communication speed such as memory field. However, there is performance degradation issue on TSV technology due to the parasitic capacitance. To deal with this problem, in this study, the parasitic capacitance with TSV design factors is analyzed using commercial tool. TSV design factors were set in three categories: size, aspect ratio, pitch. Each factor was set by dividing the range with TSV used for memory and package. Ansys electronics desktop 2021 R2.2 Q3D was used for the simulation to acquire parasitic capacitance data. DOE analysis was performed based on the reaction surface method. As a result of the simulation, the most affected factors by the parasitic capacitance appeared in the order of size, pitch and aspect ratio. In the case of memory, each element interacted, and in the case of package, it was confirmed that size * pitch and size * aspect ratio interact, but pitch * aspect ratio does not interact.

• KIPS Transactions on Computer and Communication Systems
• /
• v.4 no.9
• /
• pp.327-336
• /
• 2015

Mobile game servers usually execute frequent dynamic memory allocation for generating the buffers that deal with clients requests. It causes to deteriorate the performance of game servers since it increases system workload and memory fragmentation. In this paper, we propose fixed-sized memory pool management method. Memory pool for the proposed method has a sequential memory structure based on circular linked list data structure. It solves memory fragmentation problem and saves time for searching the memory blocks which are required for memory allocation and deallocation. We showed the efficiency of the proposed method by evaluating the performance of dynamic memory allocation, through the proposed method and the memory pool management method based on boost open source library.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.45 no.2
• /
• pp.61-70
• /
• 2008

Dynamic memory allocators are used for embedded systems to increase flexibility to manage unpredictable inputs and outputs. As embedded systems generally run continuously during their whole lifetime, fragmentation is one of important factors for designing the memory allocator. To minimize fragmentation, a budgeted memory allocator that has dedicated storage for predetermined objects is proposed. A budgeting method based on a mathematical analysis is also presented. Experimental results show that the size of the heap storage can be reduced by up to 49.5% by using the budgeted memory allocator instead of a state-of-the-art allocator. The reduced fragmentation compensates for the increased code size due to budgeted allocator when the heap storage is larger than 16KB.

• Korean Journal of Materials Research
• /
• v.13 no.6
• /
• pp.352-359
• /
• 2003

In order to control the grain size, the spark plasma sintering technique is applied for the manufacturing of Cu-26.7Al-4.05AI(wt.%) shape memory alloy with pure Cu, Zn, and Al element powders. The sintering processes were carried out under different atmospheres. The sintered bodies were denser under Ar or Ar＋4%$H_2$gas atmosphere than under vacuum. With use of small-sized powders, a very small average grain size of 2∼3 $\mu\textrm{m}$ was obtained, but the single phase was not formed. With the large-sized powders the single austenitic phase was observed with the average grain size of $70∼72\mu\textrm{m}$. When the different size of raw powders was mixed, it is confirmed that the average grain size of the manufactured alloys was 15 $\mu\textrm{m}$ with single austenitic phase, but the distribution of grain size was not uniform.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.22 no.2
• /
• pp.77-82
• /
• 2022

Due to the recent advent of fast storage media, the memory management system needs to reconsider the configuring of a page unit. In this paper, we analyze the effect of the page size on memory performance as fast storage is adopted. Specifically, we analyze the TLB hit ratio and the page fault ratio as the workload and the page size are varied in desktop and smartphone environments. Our analysis shows that the influence of the page size depends on the system and workload conditions in desktop systems. However, in smartphone systems, the effect of the page size on memory performance is not large, and is not also sensitive to workloads. We expect that the analysis of this paper will be helpful in configuring the page size of given workloads under the system with fast storage media.

• Journal of information and communication convergence engineering
• /
• v.7 no.2
• /
• pp.199-202
• /
• 2009

Adaptive memory management is a serious issue in data stream management. Data stream differ from the traditional stored relational model in several aspect such as the stream arrives online, high volume in size, skewed data distributions. Data skew is a common property of massive data streams. We propose the predicted allocation strategy, which uses predictive processing to cope with time varying data skew. This processing includes memory usage estimation and indexing with timestamp. Our experimental study shows that the predictive strategy reduces both required memory space and latency time for skewed data over varying time.

• Journal of KIISE:Computer Systems and Theory
• /
• v.30 no.3_4
• /
• pp.205-212
• /
• 2003

In this paper, we propose a simple and efficient hardware-supported antialiasing algorithm and its rendering scheme. The proposed method can efficiently reduce the required memory bandwidth as well as memory size compared to a conventional supersampling when rendering 3D models. In addition, it can provide almost the same high quality scenes as supersampling does. In this paper, we have introduced the RUF (Recently Used Fragment) buffer that stores some or whole parts of a fragment or two more the merged results of fragments that recently used in color calculation. We have also proposed a color calculation algorithm to deteriorate the image quality as referencing the RUF buffer. Because of the efficiency presented in the proposed algorithm, the more number of sampling points increases the more memory saving ratio we can gain relative to the conventional supersampling. In our simulation, the proposed method can reduce the amount of memory size by 31% and the memory bandwidth by 11% with a moderate pixel color difference of 1.3% compared to supersampling for 8 sparse sampling points.

• Journal of KIISE:Computing Practices and Letters
• /
• v.15 no.5
• /
• pp.350-354
• /
• 2009

To optimize the performance of software programs, it is important to know certain hardware parameters such as the CPU speed, the cache size, the number of TLB entries, and the parameters of the memory subsystem. There exist several ways to obtain the values of various hardware parameters. Firstly. the values can be taken from the hardware manual. Secondly, the parameters can be obtained by calling functions provided by the operating systems. Finally, hardware detection programs can find the desired values. Such programs are usually executed on PC or server systems and report the CPU speed, the cache size, the number of TLB entries, and so on. However, they do not sufficiently detect the parameters of one of the most important parts of the computer concerning performance, namely the memory bank layout in the memory subsystem. In this paper, we present an algorithm to detect the memory bank parameters. We run an implementation of our algorithm on various embedded systems and compare the detected values with the real hardware parameters. The results show that the presented algorithm detects the cache size, the number of TLB entries, and the memory bank layout with high accuracy.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.13 no.1
• /
• pp.42-47
• /
• 2020

In OFDM-based very high-speed communication systems, FFT/IFFT processor should have several properties of low-area and low-power consumption as well as high throughput and low processing latency. Thus, radix-2k MDF (multipath delay feedback) architectures by adopting pipeline and parallel processing are suitable. In MDF architecture, the feedback memory which increases in proportion to the input signal word-length has a large area and power consumption. This paper presents a feedback memory size reduction method of radix-22 MDF IFFT processor for OFDM applications. The proposed method focuses on reducing the feedback memory size in the first two stages of MDF architectures since the first two stages occupy about 75% of the total feedback memory. In OFDM transmissions, IFFT input signals are composed of modulated data and pilot, null signals. In order to reduce the IFFT input word-length, the integer mapping which generates mapped data composed of two signed integer corresponding to modulated data and pilot/null signals is proposed. By simulation, it is shown that the proposed method has achieved a feedback memory reduction up to 39% compared to conventional approach.