• International journal of advanced smart convergence
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• 제6권1호
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• pp.39-43
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• 2017

As the industry grows, the amount of data grows exponentially, and data analysis using these serves as a predictable solution. As data size increases and processing speed increases, it has begun to be applied to new fields by combining artificial intelligence technology as well as simple big data analysis. In this paper, we propose a method to quickly apply a machine learning based algorithm through efficient resource allocation. The proposed algorithm allocates memory for each attribute. Learning Distinct of Attribute and allocating the right memory. In order to compare the performance of the proposed algorithm, we compared it with the existing K-means algorithm. As a result of measuring the execution time, the speed was improved.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 B
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• pp.959-961
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• 2003

In this paper, we describe implemented DMAC (Direct Memory Access Controller) architecture on Altera's $Excalibur^{TM}$ that includes industry-standard $ARM922T^{TM}$ 32-bit RISC processor core operating at 200 MHz. We implemented DMAC based on AMBA (Advanced Micro-controller Bus Architecture) AHB (Advanced Micro-performance Bus) interface. Implemented DMAC has 8-channel and can extend supportable channel count according to user application. We used round-robin method for priority selection. Implemented DMAC supports data transfer between Memory-to-Memory, Memory-to-Peripheral and Peripheral-to-Memory. The max transfer count is 1024 per a time and it can support byte, half-word and word transfer according to AHB protocol (HSIZE signals). We implemented with VHDL and functional verification using $ModelSim^{TM}$. Then, we synthesized using $LeonardoSpectrum^{TM}$ with Altera $Excalibur^{TM}$ library. We did FPGA P&R and targeting using $Quartus^{TM}$. We can use implemented DMAC module at any system that needs high speed and broad bandwidth data transfers.

• 동의생리병리학회지
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• 제35권3호
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• pp.97-103
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• 2021

Perilla frutescens (P. frutescens) is an important herb used for many purposes such as medicinal, aromatic, and functional food in Asian countries and has beneficial effects such as antioxidant activity, anti-inflammation activity, anti-depression activity, and anxiolytic activity. However, there have been no studies on the protective effect of P. frutescens extract (PFE) on amnesia in vivo. The present study aimed to investigate whether PFE protects memory deficit using a scopolamine-induced mice model and elucidate the underlying mechanisms involved. The protective effect of PFE against scopolamine-induced memory deficits was investigated using Y-maze, passive avoidance, and Morris water maze tests. Furthermore, the potential mechanisms of PFE in improving memory capabilities related to the cholinergic system and antioxidant activity were examined. PFE significantly increased spontaneous alternation in the Y-maze test, step-through latency in the passive avoidance test, and swimming time in the target quadrant in the probe test when compared to the scopolamine-treated group. Likewise, PFE significantly decreased escapes latency in the Morris water maze test. PFE could not regulate cholinergic function in acetylcholine level and acetylcholine esterase activity. However, PFE increased DPPH radical scavenging activity dose-dependently and total polyphenol content was 127.7±1.2 ㎍ GAE/mg. The results showed that the PFE could be a preventive and/or therapeutic candidate for memory and cognitive dysfunction in Alzheimer's disease.

• 대한전자공학회논문지SD
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• 제44권12호
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• pp.85-92
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• 2007

메모리 설계 기술과 제조 공정의 발전에 따라, 고집적 메모리의 생산이 본격화 되었다. 이러한 메모리의 고집적화는 복잡하고 정밀한 설계와 제조 공정을 필요로 하기 때문에, 메모리 내에 더 많은 고장을 존재할 가능성을 낳았다. 이에 따라 메모리에서 발생하는 여러 고장을 분석하고 메모리를 수리하여 공정상의 문제를 수정하기 위해, BISR(Built-In Self-Repair) 회로의 중요성이 부각되고 있다. 본 논문에서는 주어진 예비 메모리를 효율적으로 사용하여 고장이 발생한 메모리를 효과적으로 수리할 수 있는 메모리 내장형 자체 수리 회로의 구조와 그 방법론에 대해서 소개하고자 한다. 제안하는 자체 수리 회로는 sign bit이라는 추가적인 저장 장치를 이용하여 메모리 수리를 수행한다. 이는 기존에 비해 좀 더 향상된 성능을 가지고 있다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제17권3호
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• pp.896-915
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• 2023

The network function virtualization (NFV) uses virtualization technology to separate software from hardware. One of the most important challenges of NFV is the resource management of virtual network functions (VNFs). According to the dynamic nature of NFV, the resource allocation of VNFs must be changed to adapt to the variations of incoming network traffic. However, the significant delay may be happened because of the reallocation of resources. In order to balance the performance between delay and quality of service, this paper firstly made a compromise between VNF migration and energy consumption. Then, the long short-term memory (LSTM) was utilized to forecast network traffic. Also, the asymmetric loss function for LSTM (LO-LSTM) was proposed to increase the predicted value to a certain extent. Finally, an experiment was conducted to evaluate the performance of LO-LSTM. The results demonstrated that the proposed LO-LSTM can not only reduce migration times, but also make the energy consumption increment within an acceptable range.

• 전자공학회지
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• 제34권7호통권278호
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• pp.54-66
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• 2007

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 춘계학술발표대회
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• pp.28.2-28.2
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• 2011

Resistance random access memory (ReRAM) is a promising candidate for next-generation nonvolatile memory because of its advantageous qualities such as simple structure, superior scalability, fast switching speed, low-power operation, and nondestructive readout. We investigated the resistive switching behavior of tantalum oxide that has been widely used in dynamic random access memories (DRAM) in the present semiconductor industry. As a result, it possesses full compatibility with the entrenched complementary metal-oxide-semiconductor processes. According to previous studies, TiN is a good oxygen reservoir. The TiN top electrode possesses the specific properties to control and modulate oxygen ion reproductively, which results in excellent resistive switching characteristics. This study presents fully room temperature fabricated the TiN/$TaO_x$/Pt devices and their electrical properties for nonvolatile memory application. In addition, we investigated the TiN electrode dependence of the electrical properties in $TaO_x$ memory devices. The devices exhibited a low operation voltage of 0.6 V as well as good endurance up to $10^5$ cycles. Moreover, the benefits of high devise yield multilevel storage possibility make them promising in the next generation nonvolatile memory applications.

• 전자공학회논문지
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• 제51권12호
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• pp.72-82
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• 2014

최근 스마트폰, 태블릿 PC, SSD(Solid State Drive)의 보급률 증가로 메모리 반도체 산업시장의 규모는 지속적으로 증가하고 있다. 또한 최근 SSD시장에 TLC NAND-형 플래시 메모리 제품의 출시로 인해 TLC NAND-형 플래시 메모리의 수요가 점차 증가할 것으로 예상된다. SLC NAND 플래시 메모리는 많은 연구가 진행되었지만 TLC NAND 플래시 메모리는 연구가 진행되지 않고 있다. 또한 NAND-형 플래시 메모리는 고가의 외부장비에 의존하여 테스트를 하고 있다. 따라서 본 논문은 기존에 제안된 SLC NAND 플래시 메모리와 MLC NAND 플래시 메모리 테스트 알고리즘을 TLC NAND 플래시 메모리에 맞게 알고리즘과 패턴을 수정하여 적용하고 고가의 외부 테스트 장비 없이 자체 테스트 수행이 가능한 구조를 제안한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.269-274
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• 1999

As the semiconductor industry enters the next century, we are facing to the technological changes and challenges. Optical lithography has driven by the miniaturisation of semiconductor devices and has been accompanied by an increase in wafer productivity and performance through the reduction of the IC image geometries. In the last decade, DRAM(Dynamic Random Access Memories) have been quadrupoling in level of integration every two years. Korean chip makers have been produced the memory devices, mainly DRAM, which are the driving force of IC＇s(Integrated Circuits) development and are the technology indicator for advanced manufacturing. Therefore, Korean chip makers have an important position to predict and lead the patterning technology. In this paper, we will be discussed the limitations of the optical lithography, such as KrF and ArF. And, post optical lithography technology, such as E-beam lithography, EUV and E-beam Projection Lithography shall be introduced.

• 한국컴퓨터정보학회논문지
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• 제25권2호
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• pp.21-29
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• 2020

IT 산업 환경에서 모바일 데이터의 수요 증가로 인해 NAND 플래시 메모리의 사용이 지속적으로 증가하고 있다. 하지만, 플래시 메모리의 소거 동작은 긴 대기 시간과 높은 소비 전력을 요구하여 각 셀의 수명을 제한한다. 따라서 쓰기와 삭제 작업을 자주 수행하면 플래시 메모리의 성능과 수명이 단축된다. 이런 문제를 해결하기 위해 디스크 버퍼를 이용, 플래시 메모리에 할당되는 쓰기 및 지우기 연산을 감소시켜 플래시 메모리의 성능을 향상시키는 기술이 연구되고 있다. 본 논문에서는 쓰기 횟수를 최소화하기 위한 CPWL 기법을 제안한다. CPWL 기법은 버퍼 메모리 액세스 패턴에 따라 읽기 및 쓰기 페이지를 나누어 관리한다. 이렇게 나뉜 페이지를 정렬하여 쓰기 횟수를 줄이고 결과적으로 플래시 메모리의 수명을 늘리고 에너지 소비를 감소시킨다.