• Title/Summary/Keyword: memory characteristics

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A study on dynamic behavior of bidirectional SMA Actuator with forced-cooling (강제공냉 차동식 형상기억합금 액츄에이터의 동작특성에 관한 연구)

  • 정상화;김현욱;차경래
    • Proceedings of the Korean Society of Machine Tool Engineers Conference
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    • 2003.10a
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    • pp.47-52
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    • 2003
  • In the recent years, as the research and the development of micro and precision machinery become active, the interest of micro actuators using SMA(Shape Memory Alloy) has been increased. The dynamic characteristic analysis of SMA is necessary for actuator application and many common researches report the material characteristics of SMA sufficiently. However, the research on dynamic characteristics is very deficient. In this paper, the helical spring are fabricated with NiTi SMA wire of high resistivity. The force, response speed, temperature, and displacement are measured by digital force gauge, infrared thermometer, and laser displacement sensor so that the dynamic characteristics of this SMA is analyzed. Also, bidirectional actuator was fabricated and experimented fir its performance.

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A study on the Improvement of the Performance of Biodirectional SM Actuator (NiTi 형상기억합금을 이용한 차동식 액츄에이터의 동작성능 향상을 위한 연구)

  • Jeong, Sang-Hwa;Kim, Hyon-Uk;Cha, Kyoung-Rae;Song, Suk;Shin, Byung-Su;Lee, Kyoung-Hyoung
    • Proceedings of the Korean Society of Machine Tool Engineers Conference
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    • 2003.04a
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    • pp.346-351
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    • 2003
  • In the recent years, as the research and the development of micro and precision machinery become active, the interest of micro actuators using SMA(Shape Memory Alloy) has been increased. The dynamic characteristic analysis of SMA is necessary for actuator application and many common researches report the material characteristics of SMA sufficiently. However, the research on dynamic characteristics is very deficient. In this paper, the helical spring are fabricated with NiTi SMA wire of high resistivity. The force, response speed, temperature, and displacement are measured by digital force gauge, infrared thermometer, and laser displacement sensor so that the dynamic characteristics of this SMT is analyzed. Also, bidirectional actuator was fabricated and experimented for its performance

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The Function of Memory CD8+ T Cells in Immunotherapy for Human Diseases

  • Hanbyeul Choi;Yeaji Kim;Yong Woo Jung
    • IMMUNE NETWORK
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    • v.23 no.1
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    • pp.10.1-10.16
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    • 2023
  • Memory T (Tm) cells protect against Ags that they have previously contacted with a fast and robust response. Therefore, developing long-lived Tm cells is a prime goal for many vaccines and therapies to treat human diseases. The remarkable characteristics of Tm cells have led scientists and clinicians to devise methods to make Tm cells more useful. Recently, Tm cells have been highlighted for their role in coronavirus disease 2019 vaccines during the ongoing global pandemic. The importance of Tm cells in cancer has been emerging. However, the precise characteristics and functions of Tm cells in these diseases are not completely understood. In this review, we summarize the known characteristics of Tm cells and their implications in the development of vaccines and immunotherapies for human diseases. In addition, we propose to exploit the beneficial characteristics of Tm cells to develop strategies for effective vaccines and overcome the obstacles of immunotherapy.

Effect of Annealing Atmosphere on the La2O3 Nanocrystallite Based Charge Trap Memory

  • Tang, Zhenjie;Zhao, Dongqiu;Hu, Huiping;Li, Rong;Yin, Jiang
    • Transactions on Electrical and Electronic Materials
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    • v.15 no.2
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    • pp.73-76
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    • 2014
  • $Pt/Al_2O_3/La_2Si_5O_x/SiO_2/Si$ charge trap memory capacitors were prepared, in which the $La_2Si_5O_x$ film was used as the charge trapping layer, and the effects of post annealing atmospheres ($NH_3$ and $N_2$) on their memory characteristics were investigated. $La_2O_3$ nanocrystallites, as the storage nodes, precipitated from the amorphous $La_2Si_5O_x$ film during rapid thermal annealing. The $NH_3$ annealed memory capacitor showed higher charge storage performances than either the capacitor without annealing or the capacitor annealed in $N_2$. The memory characteristics were enhanced because more nitrogen was incorporated at the $La_2Si_5O_x/SiO_2$ interface and interfacial reaction was suppressed after the $NH_3$ annealing treatment.

Performance Analysis of Clustering and Non-clustering Methods in Flash Memory Environment (플래시 메모리 환경에서 클러스터링 방법과 비 클러스터링 방법의 성능 분석)

  • Bae, Duck-Ho;Chang, Ji-Woong;Kim, Sang-Wook
    • Journal of KIISE:Computing Practices and Letters
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    • v.14 no.6
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    • pp.599-603
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    • 2008
  • Flash memory has its unique characteristics: the write operation is much more costly than the read operation and in-place updating is not allowed. In this paper, we analyze how these characteristics of flash memory affect the performance of clustering and non-clustering in record management, and shows that non-clustering is more suitable in flash memory environment, which does not hold in disk environment. Also, we discuss the problems of the existing non-clustering method, and identify considerable designing factors of record management method in flash memory environment.

Nonvolatile Memory Characteristics of Double-Stacked Si Nanocluster Floating Gate Transistor

  • Kim, Eun-Kyeom;Kim, Kyong-Min;Son, Dae-Ho;Kim, Jeong-Ho;Lee, Kyung-Su;Won, Sung-Hwan;Sok, Jung-Hyun;Hong, Wan-Shick;Park, Kyoung-Wan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.1
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    • pp.27-31
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    • 2008
  • We have studied nonvolatile memory properties of MOSFETs with double-stacked Si nanoclusters in the oxide-gate stacks. We formed Si nanoclusters of a uniform size distribution on a 5 nm-thick tunneling oxide layer, followed by a 10 nm-thick intermediate oxide and a second layer of Si nanoclusters by using LPCVD system. We then investigated the memory characteristics of the MOSFET and observed that the charge retention time of a double-stacked Si nanocluster MOSFET was longer than that of a single-layer device. We also found that the double-stacked Si nanocluster MOSFET is suitable for use as a dual-bit memory.

A study on characteristics of the scaled SONOSFET NVSM for Flash memory (플래시메모리를 위한 scaled SONOSFET NVSM 의 프로그래밍 조건과 특성에 관한 연구)

  • 박희정;박승진;홍순혁;남동우;서광열
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2000.07a
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    • pp.751-754
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    • 2000
  • When charge-trap SONOS cells are used flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM cells were fabricated using 0.35$\mu\textrm{m}$ standard memory cell embedded logic process including the ONO cell process. based on retrograde twin-well, single-poly, single metal CMOS process. The thickness of ONO triple-dielectric for memory cell is tunnel oxide of 24${\AA}$, nitride of 74 ${\AA}$, blocking oxide of 25 ${\AA}$, respectively. The program mode(Vg: 7,8,9 V, Vs/Vd: -3 V, Vb: floating) and the erase mode(Vg: -4,-5,-6 V, Vs/Vd: floating, Vb: 3V) by modified Fowler-Nordheim(MFN) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation($\Delta$Vth, S, Gm) characteristics than channel MFN tunneling operation. Also the program inhibit conditions of unselected cell for separated source lines NOR-tyupe flash memory application were investigated. we demonstrated that the program disturb phenomenon did not occur at source/drain voltage of 1 V∼4 V and gate voltage of 0 V∼4.

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Algorithmic GPGPU Memory Optimization

  • Jang, Byunghyun;Choi, Minsu;Kim, Kyung Ki
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.4
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    • pp.391-406
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    • 2014
  • The performance of General-Purpose computation on Graphics Processing Units (GPGPU) is heavily dependent on the memory access behavior. This sensitivity is due to a combination of the underlying Massively Parallel Processing (MPP) execution model present on GPUs and the lack of architectural support to handle irregular memory access patterns. Application performance can be significantly improved by applying memory-access-pattern-aware optimizations that can exploit knowledge of the characteristics of each access pattern. In this paper, we present an algorithmic methodology to semi-automatically find the best mapping of memory accesses present in serial loop nest to underlying data-parallel architectures based on a comprehensive static memory access pattern analysis. To that end we present a simple, yet powerful, mathematical model that captures all memory access pattern information present in serial data-parallel loop nests. We then show how this model is used in practice to select the most appropriate memory space for data and to search for an appropriate thread mapping and work group size from a large design space. To evaluate the effectiveness of our methodology, we report on execution speedup using selected benchmark kernels that cover a wide range of memory access patterns commonly found in GPGPU workloads. Our experimental results are reported using the industry standard heterogeneous programming language, OpenCL, targeting the NVIDIA GT200 architecture.

Yield Enhancement Techniques for 3D Memories by Redundancy Sharing among All Layers

  • Lee, Joo-Hwan;Park, Ki-Hyun;Kang, Sung-Ho
    • ETRI Journal
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    • v.34 no.3
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    • pp.388-398
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    • 2012
  • Three-dimensional (3D) memories using through-silicon vias (TSVs) will likely be the first commercial applications of 3D integrated circuit technology. A 3D memory yield can be enhanced by vertical redundancy sharing strategies. The methods used to select memory dies to form 3D memories have a great effect on the 3D memory yield. Since previous die-selection methods share redundancies only between neighboring memory dies, the opportunity to achieve significant yield enhancement is limited. In this paper, a novel die-selection method is proposed for multilayer 3D memories that shares redundancies among all of the memory dies by using additional TSVs. The proposed method uses three selection conditions to form a good multi-layer 3D memory. Furthermore, the proposed method considers memory fault characteristics, newly detected faults after bonding, and multiple memory blocks in each memory die. Simulation results show that the proposed method can significantly improve the multilayer 3D memory yield in a variety of situations. The TSV overhead for the proposed method is almost the same as that for the previous methods.

Research on Improving Memory of VR Game based on Visual Thinking

  • Lu, Kai;Cho, Dong Min;Zou, Jia Xing
    • Journal of Korea Multimedia Society
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    • v.25 no.5
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    • pp.730-738
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    • 2022
  • Based on visual Thinking theory, VR(virtual reality) game changes the traditional form of memory and maps the content into game elements to realize the immersive spatial memory mode. This paper analyzes the influencing factors of game design and system function construction. This paper proposes a hypothesis: with the help of visual thinking theory, VR game is helpful to improve learners' visual memory, and carries out research. The experiment sets different levels of game through empirical research and case analysis of memory flip game. For example, when judging two random cards. If the pictures are the same, it will be judged as the correct combination; if they are different, the two cards will be restored to the original state. The results are analyzed by descriptive statistical analysis and AMOS data analysis. The results show that game content using the concept of "Memory Palace", which can improve the accuracy of memory. We conclude that the use of spatial localization characteristics in flip games combining visual thinking can improve users' memory by helping users memorize and organize information in a Virtual environment, which means VR games have strong feasibility and effectiveness in improving memory.