• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.30-36
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• 2011

Three-dimensional (3D) memories using through-silicon vias (TSVs) as vertical bus across memory layers are implemented by many semiconductor companies. 3D memories are composed of known-good-dies (KGDs). If additional faults are arisen during bonding, they should be repaired. In order to enhance the yield of 3D memories with inter-die redundancies, a die-matching method is needed to effectively stack memory dies in a 3D memory. In this paper, a new die-matching method is proposed for 3D memory yield enhancement with inter-die redundancies considering additional faults arisen during bonding. Three boundary-limited conditions are used in the proposed die-matching method; they set bounds to the search spaces for selecting memory dies to manufacture a 3D memory. Simulation results show that the proposed die-matching method can greatly enhance the 3D memory yield.

• The KIPS Transactions:PartA
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• v.8A no.2
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• pp.107-116
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• 2001

A multithreaded model is a hybrid one which combines locality of execution of the von Neumann model with asynchronous data availability and implicit parallelism of the dataflow model. Much researches that have been made toward the advanced performance of multithreaded models are about the cache memory which have been proved to be efficient in the von Neumann model. To use an instruction cache or operand cache, the multithreaded models must have cache memories. If cache memories are added to the multithreaded model, they may have the disadvantage of high implementation cost in the mode. To solve these problems, we did not add cache memory but applied the method of executing the caching by using available registers of the multithreaded models. The available register-based caching method is one that use the registers which are not used on the execution of threads. It may accomplish the same effect as the cache memory. The multithreaded models can compute the number of available registers to be used during the process of the register optimization, and therefore this method can be easily applied on the models. By applying this method, we can also remove the access conflict and the bottleneck of frame memories. When we applied the proposed available register-based caching method, we found that there was an improved performance of the multithreaded model. Also, when the available-register-based caching method is compared with the cache based caching method, we found that there was the almost same execution overhead.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.254-254
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• 2011

The memories with nano-particles are very attractive because they are promising candidates for low operating voltage, long retention time and fast program/erase speed. In recent, various nano-floating gate memories with metal-oxide nanocrystals embedded in organic and inorganic layers have been reported. Because of the carrier generation in semiconductor, induced photon pulse enhanced the program/erase speed of memory device. We studied photo-induced electrical properties of these metal-oxide nanocrystal memory devices. At first, 2~10-nm-thick Sn and In metals were deposited by using thermal evaporation onto Si wafer including a channel with $n^+$ poly-Si source/drain in which the length and width are 10 ${\mu}m$ each. Then, a poly-amic-acid (PAA) was spin coated on the deposited Sn film. The PAA precursor used in this study was prepared by dissolving biphenyl-tetracarboxylic dianhydride-phenylene diamine (BPDA-PDA) commercial polyamic acid in N-methyl-2-pyrrolidon (NMP). Then the samples were cured at 400$^{\circ}C$ for 1 hour in N atmosphere after drying at 135$^{\circ}C$ for 30 min through rapid thermal annealing. The deposition of aluminum layer with thickness of 200 nm was followed by using a thermal evaporator, and then the gate electrode was defined by photolithography and etching. The electrical properties were measured at room temperature using an HP4156a precision semiconductor parameter analyzer and an Agilent 81101A pulse generator. Also, the optical pulse for the study on photo-induced electrical properties was applied by Xeon lamp light source and a monochromator system.

• Archives of design research
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• v.15 no.1
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• pp.27-36
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• 2002

To do this, study of human memory and theoretical approach on form in general is carried out to compare the types of memories and the stage of perceive theoretically to discover the relationship between psychological perceive and form. In the second please, scenario of form recognition in cultural aspect is studied through various written records to obtain unbiased critics on what a person can feel from a form through various analysis and experiment. Examples will be given on products designed on the basis of correlation with form through analysis. Through this procedure, elements of reactions on implicit and explicit is derived (Data obtained from experiments on computers and inquiries are used) Analyzed elements are than divided into, general knowledge, memories of reality and subconsciousness memories and basic mental image and user mental image and mental image of form of each products are analyzed. In the third phase, the way of adapting of the elements obtained from the analysis of implicit and explicit reaction to the field of design is predicted. Together with this, future theme this the study will be suggested. Confusions obtained from this study can be listed as below.

• The Journal of the Korea Contents Association
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• v.12 no.9
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• pp.40-47
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• 2012

Existing art, media art, accompanied by a new path of awareness and perception instrumentalized by the human body, creating a new way to watch the interaction is proposed. Western art way to create visual images of the point cloud that represented a form that is similar to the Pointage. This traditional painting techniques using digital technology means reconfiguration. In this paper, a new appreciation of fusion of aesthetic elements and digital technology, making the point cloud in the form of video. And this holographic film projection of the spectator, and gestures to interact with the video content is presented. A Process of making contents is intent planning, content creation, content production point cloud in the form of image, 3D gestures for interaction design process, go through the process of holographic film projection. Visual and experiential content of memory recall process takes place in the consciousness of the people expressed. Complete the process of memory recall, uncertain memories, memories materialized, recalled. Uncertain remember the vague shapes of the point cloud in the form of an image represented by the image. As embodied memories through the act of interaction to manipulate images recall is complete.

• Journal of IKEEE
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• v.5 no.1 s.8
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• pp.43-51
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• 2001

As the density of memories increases, unwanted interference between cells and coupling noise between bit-lines are increased. And testing high-density memories for a high degree of fault coverage can require either a relatively large number of test vectors or a significant amount of additional test circuitry. So far, conventional test algorithms have focused on faults between neighborhood cells, not neighborhood bit-lines. In this paper, a new test algorithm for neighborhood bit-line sensitive faults (NBLSFs) based on the NPSFs(Neighborhood Pattern Sensitive Faults) is proposed. And the proposed algorithm does not require any additional circuit. Instead of the conventional five-cell or nine-cell physical neighborhood layouts to test memory cells, a three-cell layout which is minimum size for NBLSFs detection is used. Furthermore, to consider faults by maximum coupling noise by neighborhood bit-lines, we added refresh operation after write operation in the test procedure(i.e.,$write{\rightarrow}\;refresh{\rightarrow}\;read$). Also, we show that the proposed algorithm can detect stuck-at faults, transition faults, coupling faults, conventional pattern sensitive faults, and neighborhood bit-line sensitive faults.

• Journal of the Korean Geographical Society
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• v.44 no.6
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• pp.779-796
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• 2009

Pimat-gil is a bystreet over 600-years old of Jong-no in Seoul that originated in the early Joseon Dynasty. This Study defines Pimat-gol (a street village) that has developed centering around Pimat-gil (alley) as a typical backlane of modern city, traces the origin and landscapes of Pimat-gol through the historical geographies of this place, and tries to name and interpret the placeness of Pimat-gol from the angles of social and cultural geography, particularly on the basis of the concept 'place memory'. As a result, the author extracts the placeness of Pimat-gol in terms of juxtaposition of three-fold layers, ie., 'space of subaltern vs. space of escape', 'space of oblivion vs. space of recollecttion and generation', and 'space of fossil vs. space of living'. In addition, the author examines the place memories which have been sedimented in this place and the contest of the place-memories by investigating these three-fold layers, and makes a proposal which would constructs another spatiality of modern city on the basis of this case.

• Journal of IKEEE
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• v.17 no.2
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• pp.168-175
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• 2013

The delay times due to the propagating of data on PCB depend on the shape and length of interconnection lines when memory controllers and high speed memories are soldered on the PCB. The dependency on the placement and routing on the PCB requires redesign of I/O logic or reconfiguration of the memory controller after the delay time is measured if the controller is programmable. In this paper, we propose architecture of configuring logic for the delay time estimation by writing and reading test patterns while initializing the memories. The configuration logic writes test patterns to the memory and reads them by changing timing until the correct patterns are read. The timing information is stored and the configuration logic configures the memory controller at the end of initialization. The proposed method enables easy design of systems using PCB by solving the problem of the mismatching caused by the variation of placement and routing of components including memories and memory controllers. The proposed method can be applied to high speed SRAM, DRAM, and flash memory.

• Journal of Families and Better Life
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• v.22 no.1
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• pp.11-25
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• 2004

This study was conducted to explore the impacts of involvement in the Vietnam War on the self-esteem of the veterans in their later lives. In this study, 14 Korean male Vietnam War veterans from 55 to 63 years old were asked about the impacts of their war experiences on their self-esteem. From the analysis of the in-depth interviews the following conclusions were drawn: First, the veterans perceived that their self-esteem improved with both internal and external impacts of their activities in Vietnam. The internal aspects that improved the veterans' self-esteem were recalling their positive memories of Vietnam War, such as being on duty at a war front for the sake of our country, doing volunteer work for the villagers, and becoming a masculine heroic figure in the family legend. The external aspects were positive attitudes and responses toward their war activities from their family, friends, and neighbors. Second, they also felt persistently frustrated with their recurring memories of involvement in killing human beings, experiences of negative family and social responses, and the side effects of herbicidal cyanide they suffer. In this article, the following suggestions were made. First, standardized images and good-will episodes of the Vietnam War need to be provided by the government, in order to improve public images on the veterans. Second, intensive adjustment programs for the families of older veterans in special needs should be developed in collaboration with various veterans' societies and family counseling institutions, so that the spouses and children can be relieved from tension-laden contacts with the veterans and prevent violent incidents.

• The Korean Journal of Archival Studies
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• no.66
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• pp.37-67
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• 2020

Recently, industrial heritages have been transformed into cultural facilities in the wake of urban Regeneration. This focus is mainly on appearance, and the explanation is often abbreviated as a master narrative, and the placeness is not sufficiently inherited. The placeness of industrial heritage contains not only historical but also personal memories. Place memory must be collected and managed in order for the placeness that can be the source of identity to be preserved and utilized. To this end, this study suggested collecting place memories based on personal life histories. Using the case of collecting Andong Station and Cheongju Tobacco Factory, the life narrative was broken down into an event and the process of reinterpreting it as a place memory was proposed to implement archiving of industrial heritage sites. This methodology means that it can be supplemented rather than replaced.