• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.259-262
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• 2012

This paper describes a delay-locked loop (DLL) that generates a 64-phase clock with the operating frequency of 125MHz. The proposed DLL use a $4{\times}8$ matrix-based delay line to improve the linearity of a delay line. The output clock with 64-phase is generated by using a CMOS multiplex and a inverted-based interpolator from 32-phase clock which is the output clock of the $4{\times}8$ matrix-based delay line. The circuit for an initial phase lock, which is independent on the duty cycle ratio of the input clock, is used to prevent from the harmonic lock of a DLL. The proposed DLL is designed using a $0.18-{\mu}m$ CMOS process with a 1.8 V supply. The simulated operating frequency range is 40 MHz to 200 MHz. At the operating frequency of a 125 MHz, the worst phase error and jitter of a 64-phase clock are +11/-12 ps and 6.58 ps, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.95-98
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• 2012

This paper describes a multiphase delay-locked loop (DLL) that generates a 32-phase output clock over the operating frequency range of 40 MHz to 280 MHz. The matrix-based delay line is used for high resolution of 1-bit delay. A calibration scheme, which improves the linearity of a delay line, is achieved by calibrating the nonlinearity of the input stage of the matrix. The multi-phase DLL is fabricated by using 0.11-${\mu}m$ CMOS process with a 1.2 V supply. At the operating frequency of 125MHz, the measurement results shows that the DNL is less than +0.51/-0.12 LSB, and the measured peak-to-peak jitter of the multi-phase DLL is 30 ps with input peak-to-peak jitter of 12.9 ps. The area and power consumption of the implemented DLL are $480{\times}550{\mu}m^2$ and 9.6 mW at the supply voltage of 1.2 V, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.137-144
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• 2013

A delay-locked loop (DLL) that generates a 32-phase clock with the operating frequency of 125 MHz is introduced. The proposed DLL uses a delay line of $4{\times}8$ matrix architecture to improve a differential non-linearity (DNL) of the delay line. Furthermore, a integral non-linearity (INL) of the proposed DLL is improved by calibrating phases of clocks that is supplied to four points of an input stage of the $4{\times}8$ matrix delay line. The proposed DLL is fabricated by using $0.11-{\mu}m$ CMOS process with a 1.2 V supply. The measured operating frequency range of the implemented DLL is 40 MHz to 280 MHz. At the operating frequency of 125MHz, the measurement results shows that the DNL and INL are +0.14/-0.496 LSB and +0.46/-0.404 LSB, respectively. The measured peak-to-peak jitter of the output clock is 30 ps when the peak-to-peak jitter of the input clock is 12.9 ps. The area and power consumption of the implemented DLL are $480{\times}550{\mu}m^2$ and 9.6 mW, respectively.

• Korean Journal of Optics and Photonics
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• v.18 no.2
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• pp.162-166
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• 2007

In this paper, we propose a WDM optical true time-delay (OTTD) beam former for phased way antenna (PAA) systems. It is composed of a delay lines matrix and a multiwavelength source with discrete DFB laser diodes. The building block of a delay lines matrix is a $2\times2$ optical MEMS switch with proper fiber-optic delay line connected between cross ports. A $4\times3$ matrix using four DFB lasers has been fabricated with unit time-delay difference of 12 ps. Maximum time-delay error was measured to be -1.74 ps and +1.14 ps at a radiation angle of $46.05^{\circ}$, corresponding to error range of $-2.87^{\circ}\sim+1.88^{\circ}$. By measuring time-delays at six different RF frequencies from 5- to 10-GHz, we verified the true time-delay characteristic of our OTTD.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.10
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• pp.95-102
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• 2003

The buffering is a promising solution to resolve the contention problem in optical network. we study the packet loss probability and the dimensioning of optical buffer using a Fiber Delay Line for variable length packet. In this paper, we study the relation between the granularity and the loss of FDL buffer in Single-Stage FDL buffer and propose the Single-Bundle Multi-Stage FDL buffer. The Multi-Stage FDL buffer is too early yet to apply to the current backbone network, considering the current technology in view of costs. but we assume that the above restriction will be resolved in these days. The appropriate number of delay and pass line for a dimensioning is based on a amount of occupied time by packets. Once more another multi-stage FDL buffer is proposed, Split-Bundle multi-stage FDL buffer. The Split-Bundle ms-FDL buffer is more feasible for a FDL buffer structure, considering not only a size of switching matrix but also a bulk of switching element. its feasibility will be demonstrated from a loss probability.

• 제어로봇시스템학회:학술대회논문집
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• 1988.10a
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• pp.219-224
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• 1988

A decentralised computational procedure is proposed for the optimal feedback gain matrix of large-scale discrete-time systems with time-delays. The constant feedback gain matrix is computed from the optimal state and input trajectries obtained hierarchically by the interaction prediction method. All the calculation in this approach are done off-line. The resulting gains are optimal for all the initial conditions. The interaction prediction method is applied to time-delay large-scale systems with general structures by extending the dimensions of coupling matices. A numerical exampie illustrates the algorithm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.2
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• pp.213-217
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• 2015

Microwave Photonic(MWP) filters capable of use a bandpass filter or a notch filter with large bandwidth have been proposed. 4-lines${\times}$2-bit fiber-optic delay lines with a unit time-delay difference of 50 ps were experimentally realized. By changing the time-delay difference and the coefficients of microwave-modulated optical signals, the bandpass and notch filters were implemented and characterized.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.12
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• pp.751-758
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• 2004

This paper presents a new method to compensate the non-linearity for matrix converter drives using PQR instantaneous Power theory. The non-linearity of matrix converter drives such as commutation delay, turn-on and turn-off time of switching device, and on-state switching device voltage drop is modelled by PQR power theory and compensated using a reference current control scheme. The proposed method does not need any additional hardware and off-line experimental measurements. The proposed compensation method is applied for high performance induction motor drives using a 3 kW matrix converter system without a speed sensor. Simulation and experimental results show the proposed method using PQR power theory Provides good compensating characteristic.

• Korean Journal of Optics and Photonics
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• v.17 no.1
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• pp.7-17
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• 2006

In this paper, we proposed an optical true time-delay (TTD) for planar phased array antennas (PAAs), which is composed of a wavelength-dependent optical true time delay (WDOTTD) followed by a wavelength-independent optical true time delay (WIOTTD). The WDOTTD is a fiber Bragg gratings (FBGs) Prism and the WDOTTD is a fiber delay-lines matrix of which each component consists of a certain length of fiber connected to cross-ports of a 2${\times}$2 MEMS switch. A 10-GHz 2-bit${\times}$4-bit two-dimensional optical TTD has been fabricated by cascading a WDOTTD with a maximum time delay of 810 ps to a WIOTTD of $\pm$50 ps. Time delay and insertion loss for each radiation angle have been measured. Time delay error for the WIOTTD has been measured to be less than $\pm$1 ps. We have also designed a two-dimensional 10-GHz PAA composed of 8${\times}$8 microstrip patch antenna elements driven by the proposed TTD. The radiation patterns of this PAA have been obtained by simulation and analyzed.

• Journal of Power System Engineering
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• v.13 no.2
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• pp.71-82
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• 2009

This paper presents a real-time haptic rendering method for a realistic force feedback in a remote environment with varying communication time-delay. The remote environment is assumed as a virtual environment based on a computer graphics, for example, on-line shopping mall, internet game and cyber-education. The properties of a virtual object such as stiffness and viscosity are assumed to be unknown because they are changed according to the contact position and/or a penetrated depth into the object. The DARMAX model based output estimator is proposed to trace the correct impedance of the virtual object in real-time. The output estimator is developed on the input-output relationship. It can trace the varying impedance in real-time by virtue of P-matrix resetting algorithm. And the estimator can trace the correct impedance by using a white noise that prevents the biased input-output information. Realistic output forces are generated in real-time, by using the inputs and the estimated impedance, even though the communication time delay and the impedance of the virtual object are unknown and changed. The generated forces trace the analytical forces computed from the virtual model of the remote environment. Performance is demonstrated by experiments with a 1-dof haptic device and a spring-damper-based virtual model.