• 전기학회논문지
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• 제67권4호
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• pp.538-542
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• 2018

In order to generate a clock source with low cost and high performance in system on chip(SoC), a relaxation oscillator with stable output characteristics according to PVT(process, voltage and temperature) fluctuation require a low area and a low power. In this paper, we propose a solution to reduce the current loss caused by parasitic components in the conventional relaxation oscillator. Since the slew rate of the bias current and the capacitor are adjusted to be the same through the proposed solution, a relaxation oscillator with low area characteristics is designed for the same clock source frequency implementation. The proposed circuit is designed using the TSMC CMOS 0.18um process. The Simulation results show that the relaxation oscillator using the proposed solution can prevent the current loss of about $279{\mu}A$ and reduce the total chip area by 20.8% compared with the conventional oscillator in the clock source frequency of 96 MHz.

• 한국정보처리학회논문지
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• 제2권1호
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• pp.66-74
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• 1995

이 논문에서는 고속 저전력 분야에 적용하기 위한 8비트, 15MHz A/D 변환기 설계 에 관해 기술한다. 2단 플래시 방식인 서브레인징 구조 A/D 변환기에서 칩 면적을 줄 이기 위해 저항의 수를 감소시킨 전압분할 회로를 설계하였다. 비교기는 80 dB의 이득, 50 MHz의 대역폭, 오프셋 전압이 0.5mV이고, 전압분할 회로의 최대오차는 1mV이다. 설계된 A/D변환기는 ＋5/-5V 공급 전압에 대해 전력소비가 150mW, 지연시간이 65ns 이다. A/D 변환기는 N-well공정을 이용하여 설계하고, 제작하였다. 제안된 변환기는 고속, 저전력, 소형 단일 칩 아날로그-디지탈 혼합 시스템 응용에 적합하다. 시뮬레이 션은 PSPICE를 이용하여 수행하였고, 1차 가공된 칩을 데스트 하였다.

• 전기학회논문지P
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• 제58권4호
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• pp.432-436
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• 2009

This paper is described that advanced study on network design of remote diagnosis system for power facilities of electric railway. In the field, it is very difficult for worker to diagnosis power facilities including catenary because workers should be maintenance on AC power supply. Therefore, to properly design on remote diagnosis system, we have searched the inside and outside of the country-related technology trends. Also we confirmed that required technologies to design interface technology required for the development of sensor devices and the USN network was designed in accordance with required skills. Throughout variety of requirements, we have development iRFS based ZA sensors and iRFM to receive data of sensor. Also CC2420 is applied as single-chip which used 2.4GHz IEEE802.15.4 compliant RF tranciver designed for low-power and low-voltage wireless applications for ZigBee communication.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 B
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• pp.1071-1073
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• 2000

The use of HDL(Hardware Description Language) is now central to the ASIC(Application Specific Integrated Circuit). HDL-based ASIC can simplify the process of development and has a competition in market because it reduce the consuming time for the design of IC(Integrated circuit) in system level. Therefore, the development of power electronics system on chip (SOC), to design microcontroller and switching logic as one chip, is required extremely for the purpose of having reliability and low cost in power electronics which is based on switching elements. The major application of SOC is variable converter, active filter inverter for induction motor. UPS and power supply with a view to reducing electro-magnetic pollution.

• 한국정보통신학회논문지
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• 제25권11호
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• pp.1627-1634
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• 2021

본 논문은 저전력 뉴럴 네트워크 가속기 SOC를 위한 아날로그 Convolution Filter용 저전력 초소형 ADC 회로 및 칩 설계 기술을 소개한다. 대부분의 딥러닝의 학습과 추론을 할 수 있는 Convolution neural network accelerator는 디지털회로로 구현되고 있다. 이들은 수많은 곱셈기 및 덧셈기를 병렬 구조로 구현하며, 기존의 복잡한 곱셉기와 덧셈기의 디지털 구현 방식은 높은 전력소모와 큰 면적을 요구하는 문제점을 가지고 있다. 이 한계점을 극복하고자 본 연구는 디지털 Convolution filter circuit을 Analog multiplier와 Accumulator, ADC로 구성된 Analog Convolution Filter로 대체한다. 본 논문에서는 최소의 칩면적와 전력소모로 Analog Accumulator의 아날로그 결과 신호를 디지털 Feature 데이터로 변환하는 8-bit SAR ADC를 제안한다. 제안하는 ADC는 Capacitor Array의 모든 Capacitor branch에 Split capacitor를 삽입하여 모든 branch의 Capacitor 크기가 균등하게 Unit capacitor가 되도록 설계하여 칩면적을 최소화 한다. 또한 초소형 unit capacitor의 Voltage-dependent capacitance variation 문제점을 제거하기 Flipped Dual-Capacitor 회로를 제안한다. 제안하는 ADC를 TSMC CMOS 65nm 공정을 이용하여 설계하였으며, 전체 chip size는 1355.7㎛², Power consumption은 2.6㎼, SNDR은 44.19dB, ENOB는 7.04bit의 성능을 달성하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 F
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• pp.2647-2649
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• 1999

Electric power system is consisted of power supply and power enable circuit. Power supply provides operating voltage with internal chip. Depending on the operating voltage, power enable circuit provides operating signal, PWREN. Because energy is obtained from signal of external station, passive transponder must have the low power consumption. In this paper, the power supply module of the low power transponder is designed and analyzed.

• 전기전자학회논문지
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• 제16권3호
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• pp.197-202
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• 2012

As more and more cores are integrated on a single chip, power consumption has become an important problem in system-on-a-chip (SoC) design. Multiple supply voltage (MSV) design is one of popular solutions to reduce power consumption. We propose a new method that determines voltage level of cores before floorplanning stage. Besides, our algorithm includes a new approach to optimize wire length and the number of level shifters without any significant decrease of power saving. In simulation, we achieved 40-52% power saving and a considerable improvement in runtime, whereas an increase in wire length and area is less than 8%.

• 한국전자파학회논문지
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• 제12권6호
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• pp.906-911
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• 2001

본 논문에서는 비화 통신을 위하여 chirp 방식을 이용한 BPSK 시스템의 LPI(low probability of intercept)와 AJ(anti jamming) 성능을 분석하였다. Chirp 방식은 주파수를 전체 확산대역 내에서 임의적으로 변화시켜 신호의 주기적인 특성을 제거하기 때문에, feature parameter인 chip rate를 검출하는데 용이한 DAM(delay and multiplier)과 반송파 주파수 검출에 용이한 SC(Squaring Circuit)에 대항하여 뛰어난 LPI 특성을 가진다. chirp parameter의 변화에 따른 LPI 특성으로 chirp duration(Tc)이 커질수록 좋은 LPI 성능을 보인다. PBNJ(partial band noise jammer)환경에서, chirp 방식이 이론적인 DSSS(Direct Sequence Spread Spectrum) 방식에 비하여 AJ 성능이 우수함을 시뮬레이션으로 확인하였다. PBNJ와 MTJ(multi-tone jammer)를 비교하였을 때, chirped BPSK 시스템이 동일 JSR(jammer to signal power ratio)에서 MTJ에 더 우수한 AJ 성능이 있다.

• Journal of electromagnetic engineering and science
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• 제9권4호
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• pp.188-193
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• 2009

A K-band low-power miniaturized planar-type hyperthermia system was developed to replace massive and expensive equipment. The system consists of a VCO with a buffer amplifier, a high-power amplifier module, a 20-dB-coupled line coupler, a chip circulator and two power detectors for signal generation, amplification and power monitoring. All these components have been implemented in planar form on two module blocks. The total size of the hyperthermia system was less than $10\times6.5\times3\;cm^3$. In order to verify the system performance, ablations were carried out on nude mice xenografted with human breast cancer. Ablation results show performance comparable to the massive components-based system. This work shows the feasibility of a low-cost miniaturized hyperthermia system for practical clinical applications.

• Journal of Power Electronics
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• 제16권1호
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• pp.340-350
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• 2016

A cascaded hybrid multilevel inverter including a reconfiguration technique for low voltage dc distribution applications is proposed in this paper. A PWM generation fault detection and reconfiguration paradigm after an inverter cell fault are developed by using only a single-chip controller. The proposed PWM technique is also modified to reduce switching losses. In addition, the proposed topology can reduce the number of required power switches compared to the conventional cascaded multilevel inverter. The proposed technique is validated by using a 3-kVA prototype. The switching losses of the proposed multilevel inverter are also investigated. The experimental results show that the proposed hybrid inverter can improve system efficiency, reliability and cost effectiveness. The efficiency of proposed system is 97.45% under the tested conditions. The proposed hybrid inverter topology is a promising method for low voltage dc distribution and can be applied for the multiple loads which are required in a data center or telecommunication building.