• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.4
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• pp.59-65
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• 2014

In this paper, in order to improve efficiency performance of power amplifiers, a mode changeable autotransformer is proposed. Efficiency performance at the low-power mode can be improved by adopting the mode changeable autotransformer. A dual-mode autotransfomrer CMOS power amplifier using a standard 0.18-${\mu}m$ CMOS process is designed in this work. Number of turns in a primary winding is re-configurated according to mode change between the high-power mode and the low-power mode. Thus, the efficiency performance of the power amplifier at each mode is optimized. EM and total circuit simulation results verify that low-power mode power added efficiency(PAE) at 24dBm output power is improved from 10.4% to 26.1% using the proposed multi-mode operation.

• Journal of the Korean Vacuum Society
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• v.5 no.1
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• pp.85-92
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• 1996

The external electricla characteristics of helicon wave plasmas were measured over a wide range of RF power and magnetic filed. External parameters. such as antenna voltage , current, phase shift, and interanl parameter, electron density were measured at 7MHz, 1mTorr Ar discharge . The equivalent discharge resistance and reactance, and the power transfer efficiency were calculated through these measurements. There are a helicon mode which produces high density plasma by helicon wave and a lowmode which produces low density plasma by capaictive electric field. In case of the helicon mode, the anternna voltage and current were lower than those of the low-mode. The phase difference between voltage and current decreased suddenly at the transition point from the low-mode to the helicon mode. Equivalent resistance and power efficiency increased and reactance decreased suddenly at the transition point. These results mean that the power transperred to plasma and the nutual coupling between the antenna and plasma increase as the mode changes from the low-mode to the helicon mode.

• ETRI Journal
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• v.38 no.5
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• pp.885-895
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• 2016

The lowest power mode (passive-standby mode) was proposed for reducing the power consumption of set-top boxes in a standby state when not receiving content. However, low-power set-top boxes equipped with the lowest power mode have been rarely commercialized because of their low-quality user experience. In the lowest power mode, they deactivates almost all of operational modules and processes, and thus require dozens of seconds for activation latency (that is, the latency for activating all modules of the set-top boxes in a standby state). They are not even updated in a standby state because they deactivate their network interfaces in a standby state. This paper proposes an adaptive standby mode scheduling method for improving the user experience of such boxes. Set-top boxes using the proposed method can analyze the activation pattern and find the frequently used time period (that is, when the set-top boxes are frequently activated). They prepare for their activation during this frequently used time period, thereby reducing the activation latency and enabling their update in a standby state.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.36-42
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• 2007

A low-power compact driver for multistandard physical layer is presented. The proposed driver achieves low power and small area through the voltage-mode driver with trans-impedance configuration and the novel hybrid driver,. In the voltage-mode driver, a trans-impedance configuration alleviates the problem of limited common-mode range of error amplifiers and the area and power overhead due to pre-amplifier. For a standard with extended output swing, only current sources are added in parallel with the voltage-mode driver, which is named a 'hybrid driver'. The hybrid architecture not only increases output swing but reduces overall driver area. The overall driver occupies $0.14mm^2$. Power consumptions under 3.3-V supply are 24.5 mW for the voltage-mode driver and 44.5 mW for the hybrid driver.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.397-398
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• 2013

Fairchild Green Mode off line buck switch for low standby power consumption and high reliability is presented. By reducing operating current and optimizing switching frequency, 20mW power consumption is achieved. High performance trans-conductance amplifier and green mode function improve the ripple and regulation in the output voltage. The conventional $FPS^{TM}$ buck and novel Fairchild buck switch are compared to show the improvement of performance. Experimental results are showed using 2W evaluation board.

• The Journal of the Korea Contents Association
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• v.10 no.12
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• pp.10-17
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• 2010

In this paper, we design digital D-PHY link chip controling DSI (Display Serial Interface) that meets MIPI (Mobile Industry Processor Interface) standard. The D-PHY supports a high-speed (HS) mode for fast data traffic and a low-power (LP) mode for control transactions. For low power consumption, the unit blocks in digital D-PHY are optionally switched using the clock gating technique. The proposed low power digital D-PHY is simulated and compared with conven tional one about power consumption on each transaction mode. As a result, power consumptions of TX, RX, and total in HS mode decrease 74%, 31%, and 50%, respectively. In LP mode, power reduction rates of TX, RX, and total are 79%, 40%, and 51.5%, separately. We implemented the low power MIPI D-PHY digital chip using $0.13-{\mu}m$ CMOS process under 1.2V supply.

• The KIPS Transactions:PartD
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• v.18D no.3
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• pp.197-204
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• 2011

Set-top Box which receives broadcasting signal and delivers it to display device such as TV usually doesn't have low-power mode, standby power mode. On the other side, most consumer electronics support standby power mode. The main reasons come from technical barriers and operational stability. Set-top box normally consumes 80~90% power of active mode even though turning off. This is much higher compared to other consumer electronics which consume less than 1W in standby power mode. However, most developed countries including Korea are enforcing the regulations which enhance energy efficiency of set-top box. This paper describes design and development of low-power set-top box. Key technologies are SoC supporting low-power mode, system hardware and software operating in separated power mode, and middleware managing the power with broadcasting system. Finally, we show energy saving expectation through development and proliferation.

• Journal of Satellite, Information and Communications
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• v.8 no.3
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• pp.10-14
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• 2013

In this paper, when applying current-mode circuit design technique showing constant power dissipation none the less operation frequency, to the low power design of dynamic voltage frequency scaling, we introduce the low power current-mode circuit design technique applying MOSFET in sub-threshold region, in order to solve the problem that has large power dissipation especially on the condition of low operating frequency. BSIM 3, was used as a MOSFET model in circuit simulation. From the simulation result, the power dissipation of the current memory circuit with sub-threshold MOSFET showed $18.98{\mu}W$, which means the consumption reduction effect of 98%, compared with $900{\mu}W$ in that with strong inversion. It is confirmed that the proposed circuit design technique will be available in DVFS using a current-mode circuit design.

• ETRI Journal
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• v.19 no.2
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• pp.35-47
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• 1997

A power amplifier operating at 3.3 V has been developed for CDMA/AMPS dual-mode cellular phones. It consists of linear GaAs power MESFET's, a new gate bias control circuit, and an output matching circuit which prevents the drain terminal of the second MESF from generating the harmonics. The relationship between the intermodulation distortion and the spectral regrowth of the power amplifier has been investigated with gate bias by using the two-tone test method and the adjacent channel leakage power ratio (ACPR) method of CDMA signals. The dissipation power of the power amplifier with a gate bias control circuit is minimized to below 1000 mW in the range of the low power levels while satisfying the ACPR of less than -26 dBc for CDMA mode. The ACPR of the power amplifier is measured to be -33 dBc at a high output power of 26 dBm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.104-110
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• 2011

A CMOS Image Sensor (CIS) mounted on mobile appliances requires low power consumption due to limitations of the battery life cycle. In order to reduce the power consumption of CIS, we propose novel power reduction techniques such as a data flip-flop circuit with leakage current elimination and a low power single slope analog-to-digital (A/D) converter with a sleep-mode comparator. Based on 0.13 ${\mu}m$ CMOS process, the chip satisfies QVGA resolution (320 ${\times}$ 240 pixels) that the cell pitch is 2.25 um and the structure is a 4-Tr active pixel sensor. From the experimental results, the performance of the CIS has a 10-b resolution, the operating speed of the CIS is 16 frame/s, and the power dissipation is 25 mW at a 3.3 V(analog)/1.8 V(digital) power supply. When we compare the proposed CIS with conventional ones, the power consumption was reduced by approximately 22% in the sleep mode, and 20% in the active mode.