• Journal of Korea Society of Industrial Information Systems
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• v.24 no.1
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• pp.31-38
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• 2019

In this paper, we develop a beamforming front end platform with pipeline circuit configuration method that can apply various clinical diagnostic applications of ultrasound image technology. Hardware design targets compression applications as well as scalable applications where power, integration levels and replication possibilities are important. Firmware design was implemented to achieve optimal FPGA parallel processing level by constructing new IP and system-oriented design environment to accelerate design productivity with maximum productivity improvement using Vivado HLS tool, which is a next generation high level synthesis tool. Former supports the high-speed management function of scan data that can create an image area arbitrarily and can be appropriately corrected and supplemented when reconfiguring or changing system specifications in the future.

• Journal of the Korea Institute of Military Science and Technology
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• v.10 no.4
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• pp.138-144
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• 2007

This paper introduces the design techniques of an IR module using the 2-D array un-cooled type infrared detector which is applied to the individual combat weapon. Considering the size and weight of the hand carried weapon system, we used a very small-sized detector and applied an adaptive temperature control algorithm so that the operation consumed with low power can be possible. We applied the AR(Auto Regressive) filter to improve the signal-to-noise ratio in a thermal image processing step. We also applied the plateau equalization and boundary enhancement techniques to improve the visibility for human visual system.

• The Transactions of the Korea Information Processing Society
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• v.1 no.4
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• pp.469-478
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• 1994

In this paper, a high speed, high resolution information processing digital- analog converter was designed for high definition color graphic, digital image signal processing, HDTV. For high speed operation, matrix type current cell array, latch which is not use pipelined, and two dimensional structure decoder using transmission gate were designed. It is adopted to fast-conversion, low-power implementation and exhibited high performance at linearity and accuracy. To reduce silicon area and to maintain resolution, current cell array composed of weighted and non-weighted current cells. In this paper, deglitching current cell design for high accuracy, new switching algorithm assert to reduce switching error. It's This circuit dissipates 130W with a 5-V power supply, and operate above 100MHz with 10 bit resolution.

• Journal of Korea Multimedia Society
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• v.19 no.2
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• pp.122-127
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• 2016

This paper propose implementation method of SoC system for efficient depth image segmentation. SoC systems are combined platform in the form of the Software and Hardware IP. In order to perform effectively, the user to determine the operation of the configuration of each part. In this paper, we implemented a segmentation of depth images taken by the infrared sensor at APU of SoC system. The proposed method efficiently implements high performance and low power in SoC system. Proposed method that using software parts of SoC system is capable to use at several depth image processing systems.

• Journal of the Institute of Convergence Signal Processing
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• v.13 no.1
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• pp.50-55
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• 2012

This paper proposes an optima] many-core processor architecture that meets the requirements of low power and high performance for different ultrasonic image resolutions in hand-held ultrasonic devices. To identify the optimal many-core architecture, seven different PE configurations are simulated for processing ultrasonic images in terms of execution performance and energy consumption. Experimental results indicate that the highest energy efficiencies are achieved at PEs=1,024, 64, and 256 for ultrasonic images at $256{\times}256$, $320{\times}240$, and $800{\times}480$ resolutions, respectively. In addition, the maximum area efficiencies are obtained at PEs=256 (for $256{\times}256$ and $800{\times}480$ image resolutions) and 64 (for $320{\times}240$ image resolution).

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.11
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• pp.4065-4083
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• 2021

Super-resolution can improve the clarity of low-resolution (LR) images, which can increase the accuracy of high-level compute vision tasks. Portable devices have low computing power and storage performance. Large-scale neural network super-resolution methods are not suitable for portable devices. In order to save the computational cost and the number of parameters, Lightweight image processing method can improve the processing speed of portable devices. Therefore, we propose the Enhanced Information Multiple Distillation Network (EIMDN) to adapt lower delay and cost. The EIMDN takes feedback mechanism as the framework and obtains low level features through high level features. Further, we replace the feature extraction convolution operation in Information Multiple Distillation Block (IMDB), with Ghost module, and propose the Enhanced Information Multiple Distillation Block (EIMDB) to reduce the amount of calculation and the number of parameters. Finally, coordinate attention (CA) is used at the end of IMDB and EIMDB to enhance the important information extraction from Spaces and channels. Experimental results show that our proposed can achieve convergence faster with fewer parameters and computation, compared with other lightweight super-resolution methods. Under the condition of higher peak signal-to-noise ratio (PSNR) and higher structural similarity (SSIM), the performance of network reconstruction image texture and target contour is significantly improved.

• Nuclear Engineering and Technology
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• v.51 no.3
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• pp.719-722
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• 2019

Gamma-ray images generally suffer from a lot of noise because of low photon detection in the gamma camera system. The purpose of this study is to improve the image quality in gamma-ray images using a gamma camera system with a fast nonlocal means (FNLM) noise reduction algorithm with an acceleration function. The designed FNLM algorithm is based on local region considerations, including the Euclidean distance in the gamma-ray image and use of the encoded information. To evaluate the noise characteristics, the normalized noise power spectrum (NNPS), contrast-to-noise ratio (CNR), and coefficient of variation (COV) were used. According to the NNPS result, the lowest values can be obtained using the FNLM noise reduction algorithm. In addition, when the conventional methods and the FNLM noise reduction algorithm were compared, the average CNR and COV using the proposed algorithm were approximately 2.23 and 7.95 times better than those of the noisy image, respectively. In particular, the image-processing time of the FNLM noise reduction algorithm can achieve the fastest time compared with conventional noise reduction methods. The results of the image qualities related to noise characteristics demonstrated the superiority of the proposed FNLM noise reduction algorithm in a gamma camera system.

• Journal of Sensor Science and Technology
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• v.23 no.5
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• pp.332-336
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• 2014

In this paper, we propose a complementary metal oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) PMOSFET-type photodetector for high-speed operation. The GBT photodetector of an active pixel sensor (APS) consists of a floating gate ($n^+$-polysilicon) tied to the body (n-well) of the PMOSFET. The p-n junction photodiode that is used in a conventional APS has a good dynamic range but low photosensitivity. On the other hand, a high-gain GBT photodetector has a high level of photosensitivity but a narrow dynamic range. In addition, the pixel size of the GBT photodetector APS is less than that of the conventional photodiode APS because of its use of a PMOSFET-type photodetector, enabling increased image resolution. A CMOS binary image sensor can be designed with simple circuits, as a complex analog to digital converter (ADC) is not required for binary processing. Because of this feature, the binary image sensor has low power consumption and high speed, with the ability to switch back and forth between a binary mode and an analog mode. The proposed CMOS binary image sensor was simulated and designed using a standard CMOS $0.18{\mu}m$ process.

• Journal of the Korea Society of Computer and Information
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• v.23 no.1
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• pp.25-32
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• 2018

In this paper, we propose an edge detection algorithm for auto focus of infrared camera. We designed and implemented the edge detection of infrared image by using a spatial filter on FPGA. The infrared camera should be designed to minimize the image processing time and usage of hardware resource because these days surveillance systems should have the fast response and be low size, weight and power. we applied the $3{\times}3$ mask filter which has an advantage of minimizing the usage of memory and the propagation delay to process filtering. When we applied Laplacian filter to extract contour data from an image, not only edge components but also noise components of the image were extracted by the filter. These noise components make it difficult to determine the focus state. Also a bad pixel of infrared detector causes a problem in detecting the edge components. So we propose an adaptive edge detection filter that is a method to extract only edge components except noise components of an image by analyzing a variance of pixel data in $3{\times}3$ memory area. And we can detect the bad pixel and replace it with neighboring normal pixel value when we store a pixel in $3{\times}3$ memory area for filtering calculation. The experimental result proves that the proposed method is effective to implement the edge detection for auto focus in infrared camera.

• Journal of Power System Engineering
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• v.13 no.4
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• pp.56-61
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• 2009

In recent years, since the continuing increase in the capacity in personal computer such as the optimal performance, high quality and high resolution image, the computer system's components produce large amounts of heat during operation. This study analyzes and investigates the ability and efficiency of a cooling system inside a computer by means of central processing unit (CPU) and power supply cooling fan. This research was conducted to enhancement of efficiency of the cooling system inside the computer by making a structure which produces different air pressures in an air inflow tube. Consequently, when temperatures of the CPU and room inside computer were compared with a general personal computer, temperatures of the tested CPU, the room and the heat sink were as low as $5^{\circ}C$, $2.5^{\circ}C$ and $7^{\circ}C$ respectively. In addition to, revolution per minute (RPM) was shown as low as 250 after 1 hour operation. This research explored the possibility of enhancing the effective cooling of high-performance computer systems.