• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
• /
• pp.457-461
• /
• 2001

Advantages of switched reluctance motor(SRM) drives make it an attractive candidate for replacing adjustable speed ac and dc drives in both industrial and consumer applications. Furthermore, a simple, low cost and robust SRM drive can be efficiently operated in the hostile environment of an automobile. Generally, the speed control of SRM has a large step change or large torque reference, the output of its PI controller is often saturated. When this happens, the integral state is not consistent with the SRM input, while may give rise to the windup phenomenon. This paper proposes anti-windup control method for SRM speed control system by hysteresis current controlled asymmetry bridge converter. The experimental results show that the speed response has much improved performance, such as a small overshoot and fast settling time at the acceleration and particulary deceleration period with braking mode.

• ETRI Journal
• /
• 제37권6호
• /
• pp.1154-1164
• /
• 2015

This paper proposes a fully sensorless driver for a permanent magnet synchronous motor (PMSM) integrated with a digital motor controller and an analog pre-driver, including sensing circuits and estimators. In the motor controller, a position estimator estimates the back electromotive force and rotor position using a sliding-mode observer. In the pre-driver, drivers for the power devices are designed with a level shifter and isolation technique. In addition, a current sensing circuit measures a three-phase current. All of these circuits are integrated in a single chip such that the driver achieves control of the speed with high accuracy. Using an IC fabricated using a $0.18{\mu}m$ BCDMOS process, the performance was verified experimentally. The driver showed stable operation in spite of the variation in speed and load, a similar efficiency near 1% compared to a commercial driver, a low speed error of about 0.1%, and therefore good performance for the PMSM drive.

• 대한전자공학회논문지SD
• /
• 제42권8호
• /
• pp.43-52
• /
• 2005

프리스케일러는 PLL(Phase Locked Loop)의 동작속도를 결정하는 중요한 부분으로서 저전력의 요구조건 또한 만족해야 한다. 따라서 프리스케일러에 적용되는 TSPC(True single pulse clocked) D-플립플롭의 설계가 중요하다. 기존의 TSPC D-플런플롭은 출력단의 글리치(glitch) 문제와 클럭의 프리차지(precharge)구간에서 내부노드의 불필요한 방전으로 인한 소비전력이 증가하는 단점이 있다. 본 논문에서는 프리차지와 방전을 위한 클럭 트랜지스터 패스를 공유함으로서 클럭 트랜지스터의 수를 감소시켰고, 입력 단에 PMOS 트랜지스터를 추가하여 프리차지 구간동안의 불필요한 방전을 차단함으로서 소비전력을 최소화하였다. 또한 출력 단에 mos 트랜지스터를 추가함으로서 글리치 문제를 제거했고, 안정적인 동작을 하는 TSPC D-플립플롭을 제안하였다. 제안된 D-플립플롭을 프리스케일러에 적용시켜 검증한 결과 3.3V에서의 최대동작주파수는 2.92GHz, 소비전력은 10.61mw로 기존의 회로$^[6]$와 비교하였을 때 PDP(Power-Delay-Product) 측면에서 $45.4\%$의 개선된 결과를 얻었다.

• 전자공학회논문지
• /
• 제50권10호
• /
• pp.239-244
• /
• 2013

본 논문에서는 고속 PMIC(Power Management Integrated Circuit) 회로를 위한 저전압 입력 보호기능을 가지는 UVLO(Under Voltage Lock Out) 기능이 탑재된 LDO(Low Drop-Out) 레귤레이터를 설계하였다. 설계된 LDO 레귤레이터는 밴드갭 기준전압 회로, 오차 증폭회로, 파워 트랜지스터 등으로 이루어지진다. LDO 레귤레이터는 5 V 전원전압으로부터 3.3 V 출력을 갖도록 설계되었으며, 저전압 입력보호 기능을 하는 UVLO 회로는 전원부와 파워 트랜지스터 사이에 삽입된다. 또한 UVLO는 5 V 구동전압에서, 하강 시 2.7 V 에서 LDO 레귤레이터 동작을 멈추게 하고, 구동전압 상승 시 4.0 V 에서 LDO 레귤레이터가 정상 동작한다. $1{\mu}m$ 20 V 고전압 CMOS 공정을 사용하여 모의실험 한 결과, 설계한 LDO 레귤레이터는 5.88 mV/V의 라인레귤레이션을 가지고, 부하전류가 0 mA에서 200 mA로 변할 때 27.5 uV/mA의 로드레귤레이션을 보였다.

• 전자공학회논문지C
• /
• 제34C권11호
• /
• pp.1-11
• /
• 1997

The transient current components of the dRAM are analyzed and the sensing current, data path operation current and DC leakage current are revealed to be the major curretn components. It is expected that the supply voltage of less than 1.5V with low VT MOS witll be used in multi-giga bit dRAM. A low voltage dual VT self-timed CMOS logic in which the subthreshold leakage current path is blocked by a large high-VT MOS is proposed. An active signal at each node of the nature speeds up the signal propagation and enables the synchronous DRAM to adopt a fast pipelining scheme. The sensing current can be reduced by adopting 8 bit prefetch scheme with 1.2V VDD. Although the total cycle time for the sequential 8 bit read is the same as that of the 3.3V conventional DRAM, the sensing current is loered to 0.7mA or less than 2.3% of the current of 3.3V conventional DRAM. 4 stage pipeline scheme is used to rduce the power consumption in the 4 giga bit DRAM data path of which length and RC delay amount to 3 cm and 23.3ns, respectively. A simple wave pipeline scheme is used in the data path where 4 sequential data pulses of 5 ns width are concurrently transferred. With the reduction of the supply voltage from 3.3V to 1.2V, the operation current is lowered from 22mA to 2.5mA while the operation speed is enhanced more than 4 times with 6 ns cycle time.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제12권3호
• /
• pp.370-376
• /
• 2012

In this work, design considerations for high-performance silicon photodetector are thoroughly investi- gated. Besides the critical dimensions of device, guidelines for process architecture are suggested. Abiding by those criteria for improving both direct-current (DC) and alternating-current (AC) perfor- mances, a high-speed low-operation power silicon photodetector based on p-i-n structure for optical interconnect has been designed by device simulation. An $f_{-3dB}$ of 80 GHz at an operating voltage of 1 V was obtained.

• 한국신재생에너지학회:학술대회논문집
• /
• 한국신재생에너지학회 2009년도 추계학술대회 논문집
• /
• pp.465-465
• /
• 2009

Wind power is one of the most reliable renewable energy sources and the installed wind turbine capacities are increasing radically every year. Although wind power has been favored by the public in general, the problem with the impact of wind turbine noise on people living in the vicinity of the turbines has been increased. Low noise wind turbine design is becoming more important as noise is spreading more adverse effect of wind turbine to public. This paper demonstrates the design of 10 kW class wind turbines, each of three blades, a rotor diameter 6.4m, a rated rotating speed 200 rpm and a rated wind speed 10 m/s. The optimized airfoil is dedicated for the 75% spanwise position because the dominant source of a wind turbine blade has been known as trailing edge noise from the outer 25% of the blade. Numerical computations are performed for incompressible flow and for Mach number at 0.145 and for Reynolds numbers at $1.02{\times}10^6$ with a lift performance, which is resistant to surface contamination and turbulence intensity. The objective in the low design process is to reduce noise emission, while sustaining high aerodynamic efficiency. Dominant broadband noise sources are predicted by semi-empirical formulas composed of the groundwork by Brooks et al. and Lowson associated with typical wind turbine operation conditions. During the airfoil redesign process, the aerodynamic performance is analyzed to minimize the wind turbine power loss. The results obtained from the design process show that the design method is capable of designing airfoils with reduced noise using a commercial 10 kW class wind turbine blade airfoil as a basis. The new optimized airfoil clearly indicates reduction of total SPL about 3 dB and higher aerodynamic performance.

• 전기전자학회논문지
• /
• 제26권4호
• /
• pp.633-638
• /
• 2022

최근 인간의 뇌를 모방한 스파이킹 뉴럴 네트워크(SNNs)의 뉴로모픽(Neuromorphic) 시스템이 주목을 받고 있다. 뉴로모픽 기술은 인지 응용과 처리 과정에서 속도가 빠르고 전력 소모가 적다는 장점이 있다. SNNs 기반의 저항성 랜덤 엑세스 메모리(RRAM) 은 병렬 연산을 위한 가장 효율적인 구조이며 스파이크 타이밍 종속 가소성(STDP)의 점진적인 스위칭 동작을 수행한다. 시냅스 소자 동작으로서의 RRAM은 저 전력 프로세싱과 다양한 메모리 상태를 표현한다. 하지만, RRAM 소자의 통합은 높은 스위칭 전압 및 전류를 유발하여 높은 전력 소비를 초래한다. RRAM의 동작 전압을 낮추기 위해서는 스위칭 레이어와 금속 전극의 신소재를 개발하는 것이 중요하다. 본 연구에서는 스위칭 전압을 낮추기 위해 전기적, 기계적 특성이 우수한 단일 벽 탄소나노튜브(SWCNTs)를 갖는 (Metal/Al₂O₃/HfO_x/SWCNTs/N+silicon, MOCS)라는 최적화된 새로운 구조를 제안하였다. 따라서 SWCNTs 기반 멤리스터의 점진적인 스위칭 동작 및 저 전력 I/V 곡선의 향상을 보여준다.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• 제16권4호
• /
• pp.1330-1350
• /
• 2022

As a preprocessing operation of transmitter antennas, the hybrid precoding is restricted by the limited computing resources of the transmitter. Therefore, this paper proposes a novel hybrid precoding that guarantees the communication efficiency with low complexity and a fast computational speed. First, the analog and digital precoding matrix is derived from the maximum eigenvectors of the channel matrix in the sub-connected architecture to maximize the communication rate. Second, the extended power iteration (EPI) is utilized to obtain the maximum eigenvalues and their eigenvectors of the channel matrix, which reduces the computational complexity caused by the singular value decomposition (SVD). Third, the Aitken acceleration method is utilized to further improve the convergence rate of the EPI algorithm. Finally, the hybrid precoding based on the EPI method and the Aitken acceleration algorithm is evaluated in millimeter-wave (mmWave) massive multiple-input and multiple-output (MIMO) systems. The experimental results show that the proposed method can reduce the computational complexity with the high performance in mmWave massive MIMO systems. The method has the wide application prospect in future wireless communication systems.

• International Journal of Control, Automation, and Systems
• /
• 제5권6호
• /
• pp.652-662
• /
• 2007

This paper presents a new and simple method for sensorless operation of matrix converter drives using a constant air-gap flux and the imaginary power flowing to the motor. To improve low-speed sensorless performance, the non-linearities of a matrix converter drive such as commutation delays, turn-on and turn-off times of switching devices, and on-state switching device voltage drop are modeled using PQR transformation and compensated using a reference current control scheme. The proposed compensation method is applied for high performance induction motor drives using a 3 kW matrix converter system. Experimental results are shown to illustrate the feasibility of the proposed strategy.