• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.10A
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• pp.776-783
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• 2009

Current-cut circuit is an effective method to obtain low power consumption in wireless communication systems as high speed OFDM. For the operation of current-mode FFT LSI with analog signal processing essentially requires current-mode serial-to-parallel/parallel-to-serial converter with multi input and output structure. However, the Hold-mode operation of current-mode serial-to-parallel/parallel-to-serial converter has unnecessary power consumption. We propose a novel current-mode serial-to-parallel/parallel-to-serial converter with current-cut circuit and full chip simulation results agree with experimental data of low power consumption. The proposed current-mode serial-to-parallel/parallel-to-serial converter promise the wide application of the current-mode analog signal processing in the field of low power wireless communication LSI.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.850-853
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• 2005

This paper presents issues of display hardware architecture, relating to memory, display driver IC architecture, and chip-to-chip interface. To achieve a low power and low cost mobile phone, not only the display architecture must be carefully selected, but also the driver-ICs optimized to accommodate the different modes of operation found in typical handheld devices. The technique of forming a photo sensor in each pixel using TFT and display module architecture are developed to add multi functions in display such as fingerprint recognition, image scanning, and integrated touch screen. Detailed architectures of IC partitioning, high-speed serial interface, D/A converter, and multi functions such as fingerprint recognition and image scanning using photo sensors are important to a power optimized system.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.567-570
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• 2002

The LVDS (Low Voltage Differential Signaling) I/O cells, fully compatible with ANSI TIA/ EIA-644 LVDS standard, are designed using a 0.35${\mu}m$ standard CMOS technology. With a single 3V supply, the core cells operate at 1.34Gbps and power consumption of the output driver and the input receiver is 10. 5mW and 4.2mW, respectively. In the output driver, we employ the DCMFB (Dynamic Common-Mode FeedBack) circuit which can control the DC offset voltage of differential output signals. The SPICE simulation result of the proposed output driver shows that the variation of the DC offset voltage is 15.6% within a permissible range. In the input receiver, the proposed dual input stage with a positive feedback latch covers rail-to-rail input common-mode range and enables a high-speed, low-power operation. 5-channels of the proposed LVDS I/O pair can handle display data up to 8-bit gray scale and UXGA resolution.

• Proceedings of the KSR Conference
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• 2009.05b
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• pp.585-592
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• 2009

The performance of screw compressor depends on lots of design parameters of rotor profile, such as length of seal line, wrap angle, blow hole, suction and discharge port size, number of rotor lobe, etc. The optimum rotor profile makes it possible to increase the compression efficiency with low energy consumption, and to minimize the loss of power. In this research, a new rotor profile design and performance analysis are done by computer simulation. It is expected that the volumetric efficiency is improved because the internal leakage is reduced due to the minimization of blow hole and clearance, and the stiffness of rotors is increased due to the reduction of length to diameter ratio. Also, the specific power consumption will be secured for use ranging from low to high operation speed.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.114-116
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• 2007

Mechanical spring and hydraulic pressure operated mechanisms are applied in most of today's High Voltage Gas Insulated Switchgear(GIS)s. This paper proposes a new type of operation mechanism for GIS circuit breakers rated at 245kV and 40kA. The Motor-Direct-Drive-Mechanism (MDDM) has many advantages compared to conventional operating mechanisms. It has a very simple structure with only one moving part, low mechanical stress and audible noise. It also allows monitoring, operation speed control and self-diagnosis functions.

• Journal of Power Electronics
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• v.16 no.3
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• pp.1076-1086
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• 2016

PI controllers are one of the most widely used controllers in industrial control systems due to their simple algorithms and stability. The parameters K_p and K_i determine the performance of the system response. The response is expected to improve by increasing the gain of the PI controller. However, too large a gain will accelerate the speed response and cause vibrations, which is not what is expected. This paper proposes a way to suppress vibrations by detecting the vibration frequency and extracting the vibration signal as a compensation to the speed feedback. Additionally, in order to improve its disturbance rejection ability, a low-order disturbance observer is proposed. This paper also explains the operation principle of the proposed method by analyzing the transfer function and it describes the design of the controller parameters in detail. Simulation and experimental results are provided to verify the merits of the proposed method. These results also show the good performance of the proposed method. It has a rapid response and suppresses vibrations.

• The KIPS Transactions:PartA
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• v.9A no.1
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• pp.93-98
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• 2002

This paper introduces the design of high-speed analog-to-digital converter (ADC) for hard disk drive (HDD) read channel applications. This circuit is bated on fast regenerative autozero comparator for high speed and low-error rate comparison operation, and Double Speed Dual ADC (DSDA) architecture for efficiently increasing the overall conversion speed of ADC. A new type of thermometer-to-binary decoder appropriate for the autozero architecture is employed for no glitch decoding, simplifying the conventional structure significantly. This ADC is designed for 6-bit resolution, 800 Msample/s maximum conversion rate, 390 mW power dissipation, one clock cycle latency in 0.65 m CMOS technology.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.05a
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• pp.21-23
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• 2013

Static Random Access Memory (SRAM) using CMOS technology has many advantages. It does not need to refresh every certain time, as a result, the speed of SRAM is faster than Dynamic Random Access Memory (DRAM). This is the reason why SRAM is widely used in almost processors and system on chips (SoC) which require high processing speed. Two basic operations of SRAM are read and write. We consider two basic factors, including the accuracy of read and write operations and the speed of these operations. In our paper, we propose the read and write assist circuits for SRAM. By adding a power control circuit in SRAM, the write operation performed successfully with low error ratio. Moreover, the value in memory cells can be read correctly using the proposed pre-charge method.

• Journal of Sensor Science and Technology
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• v.23 no.5
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• pp.332-336
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• 2014

In this paper, we propose a complementary metal oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) PMOSFET-type photodetector for high-speed operation. The GBT photodetector of an active pixel sensor (APS) consists of a floating gate ($n^+$-polysilicon) tied to the body (n-well) of the PMOSFET. The p-n junction photodiode that is used in a conventional APS has a good dynamic range but low photosensitivity. On the other hand, a high-gain GBT photodetector has a high level of photosensitivity but a narrow dynamic range. In addition, the pixel size of the GBT photodetector APS is less than that of the conventional photodiode APS because of its use of a PMOSFET-type photodetector, enabling increased image resolution. A CMOS binary image sensor can be designed with simple circuits, as a complex analog to digital converter (ADC) is not required for binary processing. Because of this feature, the binary image sensor has low power consumption and high speed, with the ability to switch back and forth between a binary mode and an analog mode. The proposed CMOS binary image sensor was simulated and designed using a standard CMOS $0.18{\mu}m$ process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.