• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.86-89
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• 2002

A new design approach for realising low-power low-voltage high-Q high-order RE bandpass filter is proposed. Based on the gyrator-C inductor topology, a 2$\^$nd/-order biquadratic bandpass filter can be realised by adding a series capacitor to the input port of the gyrator. High-Q 2$\^$nd/-order and 4$\^$th/-order fully differential RF bandpass filters operating in the 2.4-㎓ ISM (Industrial, scientific and medical) frequency band under a 2-V single power supply voltage with low power dissipation are reported.

• 전자공학회논문지C
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• 제34C권11호
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• pp.12-19
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• 1997

In this paper, we present a logic synthesis algorithm for low powr design fo combinational circuits. The proposed algorithm reduces power dissipation by eliminating unnecessary signal transitions. The proposed algorithm restructures a given circuit by using a kernel as prediction logic in a precomputation-based scheme such that switching activity of circuit can be minimized. Experimental results show that the system is efficient for low power design of combinational circuits.

• Steel and Composite Structures
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• 제43권1호
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• pp.55-66
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• 2022

To develop high-efficiency lateral force resistance components for high-rise buildings, a novel energy dissipation shear wall with concrete-filled steel tubular (CFST) column elements was proposed. An energy dissipation shear wall specimen with CFST column elements (GZSW) and an ordinary reinforced concrete shear wall (SW) were constructed, and experimented by low-cycle reversed loading. The mechanical characteristics of these two specimens, including the bearing capacity, ductility, energy dissipation, and stiffness degradation process, were analyzed. The finite-element model of the GZSW was established by ABAQUS. Based on this finite-element model, the effect of the placement of steel-plate energy dissipation connectors on the seismic performance of the shear wall was analyzed, and optimization was performed. The experiment results prove that, the GZSW exhibited a superior seismic performance in terms of bearing capacity, ductility, energy dissipation, and stiffness degradation, in comparison with the SW. The results calculated by the ABAQUS finite-elements model of GZSW corresponded well with the results of experiment, and it proved the rationality of the established finite-elements model. In addition, the optimal placement of the steel-plate energy dissipation connectors was obtained by ABAQUS.

• ETRI Journal
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• 제33권6호
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• pp.880-886
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• 2011

With the introduction of high-current 8-inch solar cells, conventional Schottky bypass diodes, usually adopted in photovoltaic (PV) panels to prevent the hot spot phenomenon, are becoming ineffective as they cause relatively high voltage drops with associated undue power consumption. In this paper, we present the architecture of an active circuit that reduces the aforementioned power dissipation by profitably replacing the bypass diode through a power MOS switch with its embedded driving circuitry. Experimental prototypes were fabricated and tested, showing that the proposed solution allows a reduction of the power dissipation by more than 70% compared to conventional Schottky diodes. The whole circuit does not require a dedicated DC power and is fully compatible with standard CMOS technologies. This enables its integration, even directly on the panel, thereby opening new scenarios for next generation PV systems.

• ETRI Journal
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• 제30권3호
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• pp.412-420
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• 2008

A new scan partition architecture to reduce both the average and peak power dissipation during scan testing is proposed for low-power embedded systems. In scan-based testing, due to the extremely high switching activity during the scan shift operation, the power consumption increases considerably. In addition, the reduced correlation between consecutive test patterns may increase the power consumed during the capture cycle. In the proposed architecture, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the spectrum of unspecified bits in the test cubes. To optimize the proposed process, a novel graph-based heuristic to partition the scan chain into several segments and a technique to increase the number of don't cares in the given test set have been developed. Experimental results on large ISCAS89 benchmark circuits show that the proposed technique, compared to the traditional full scan scheme, can reduce both the average switching activities and the average peak switching activities by 92.37% and 41.21%, respectively.

• 정보처리학회논문지:컴퓨터 및 통신 시스템
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• 제9권10호
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• pp.213-220
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• 2020

높은 사양이 필요한 하드웨어 기반의 모바일 및 IoT 임베디드 시스템은 저전력과 성능에 중요한 이슈를 갖고 있다. 이는 전력 소비로 발열량 증가 및 기기의 수명 단축 문제가 발생된다. 이러한 환경에서 소프트웨어도 제한된 전력, 메모리 등에서 안정적인 동작을 수행해야하므로 디바이스의 소비전력이 증가한다. 이를 해결하고자, 코드 관점에서 성능을 저하시키는 모듈을 식별하고, 그 모듈의 전력 최소화를 통한 성능 개선 가시화 방법을 제안한다. 이는 코드 가시화를 통해 복잡한 모듈(특히 Cyclomatic complexity, Coupling & Cohesion)을 식별하고, 저전력 코드 패턴화와 성능 코드를 간결화 한다. 이런 코드로 소비전력을 감소 및 성능 개선 함으로써 코드의 품질을 최적화 할 수 있다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1019-1022
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• 2003

This paper has proposed a 4- bit 20MHz Flash A/D converter design available analog signal processing and realized its intergrated circuit. The parallel comparison method A/D converter quantized analog signals swiftly using various converters. Also this theme has designed economic power dissipation circuit using a preamplifier of low volt & power CMOS comparator. Also the system was fabricated by Hynix 0.35um CMOS process.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.149-152
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• 2001

In this paper, a 1.5V 2㎓ low-power peak detector is presented. Analyzing the designed peak detector circuit which is composed with two NMOSs, two diodes, and two capacitors, the detection characteristic relationships are derived. The simulation results with SPICE for 2㎓ pulse signals and sinusoidal signals on the 1.5V supply voltages show the good detection characteristics for input signal levels of 50㎷~500㎷, and show very small power dissipation of 0.332㎽.

• 전자공학회논문지B
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• 제33B권4호
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• pp.52-62
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• 1996

In this paper, a new continuous-time current-mode integrator as basic building block of the low-voltage analog current-mode active filters was proposed. Compared to the current-mode integrator which was proposed by Zele, the proposed current-mode integrator had higher unity gain frequency and output impedance in addition to lower power dissipation. And also, a current-mode third-order lowpass active filter was designed with the proposed current-mode integrator. The designed circuits were fabricated using the ORBIT's 1.2.mu.m double-poly double-metal CMOS n-well process. The experimental resutls of the active filter designed and fabricated for this research have shown that it has the performance of 44.5MHz cutoff frequency, 3.3mW power dissipation and the third-order active filter area was 0.12mm$^{2}$.

• 대한전자공학회논문지SD
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• 제41권10호
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• pp.9-16
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• 2004

유한상태기의 상태할당은 이로부터 구현되는 순차회로의 속도, 면적, 테스팅 및 소비전력에 큰 영향을 미친다. 본 논문에서는 상태변수 그룹들 사이에 상호 의존성(dependency)을 최소화하여 테스팅 및 전력소모를 개선하기 위한 m-블록 분할을 이용한 새로운 상태할당 기술을 소개한다. 제안된 알고리듬은 상태들을 그룹으로 나누어 상태변수의 상호의존성을 줄이고, 상태천이 확률에 의해 결정된 무게인자에 따라 상태 간 상태변수의 변화를 최소로하는 코드를 할당하여 상태 천이시 스위칭 횟수를 줄인다. 즉 피드백 순환의 길이와 수는 상태 변수들 간에 최소 전환 활동으로 감소됩니다 벤치마크 회로에 대한 실험결과는 테스팅 및 소비전력이 현저히 개선되었음을 확인하였다.