• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.1
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• pp.118-124
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• 2007

This paper presents the effects of the injected number and amplitude of impulse current on the service life of ZnO varistors for low voltages. To analyze the effects of lightning impulse currents on the performance of ZnO varistors, the measurements of resistive leakage current and power dissipation at the power frequency ac voltage before and after the injections of the $8/20[{\mu}s]$ impulse currents were made. As a consequence, the duration and amplitude of resistive leakage current flowing through ZnO varistor were increased with increasing the number of injections of the $8/20[{\mu}s]$ impulse currents. It is desirable that the service life of ZnO varistors should be evaluated as a function of the number and amplitude of lightning impulse current.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.28-35
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• 2007

In this paper, an ultra low voltage SRAM design method based on dual-boosted cell bias technique is described. For each read/write cycle, the wordline and cell power node of the selected SRAM cells are boosted into two different voltage levels. This enhances SNM(Static Noise Margin) to a sufficient amount without an increase of the cell size, even at sub 1-V supply voltage. It also improves the SRAM circuit speed owing to increase of the cell read-out current. The proposed design technique has been demonstrated through 0.8-V, 32K-byte SRAM macro design in a $0.18-{\mu}m$ CMOS technology. Compared to the conventional cell bias technique, the simulation confirms an 135 % enhancement of the cell SNM and a 31 % faster speed at 0.8-V supply voltage. This prototype chip shows an access time of 23 ns and a power dissipation of $125\;{\mu}W/Hz$.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.20-26
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• 1999

A CMOS 6-bit 100MSPS ADC for DBS receiver is designed. The proposed ADC is composed of folding block, latch block, and digital block. The cascode interpolating block and kickback reduced latch are proposed with a high speed architecture. To verify the performance of ADC, simulations are carried out by HSPICE. The ADC achieves a clock frequency of 100MHz with a power dissipation of 40mW for 3 V supply voltage. The active chip area is $1500{\mu}m{\times}1000{\mu}m$with $0.65{\mu}m$ 2-poly 2-metal CMOS process. Further, INL and DNL are within ${\pm}0.6LSB$, ${\pm}0.5LSB$, respectively. SNDR is about 33dB at 10MHz input frequency.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.4
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• pp.35-41
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• 2016

Ceramic-metal based high power LED array package was developed via thick film LTCC technology using a glass-ceramic insulation layer and a silver conductor patterns directly printed on the aluminum heat sink substrate. The thermal resistance measurement using thermal transient tester revealed that ceramic-metal base LED package exhibited a superior heat dissipation property to compare with the previously known packaging method such as FR-4 based MCPCB. A prototype LED package sub-module with 50 watts power rating was fabricated using a ceramic-metal base chip-on-a board technology with minimized camber deformation during heat treatment by using partially covered glass-ceramic insulation layer design onto the aluminum heat spread substrate. This modified circuit design resulted in a camber-free packaging substrate and an enhanced heat transfer property compared with conventional MCPCB package. In addition, the partially covered design provided a material cost reduction compared with the fully covered one.

• Journal of Sensor Science and Technology
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• v.1 no.2
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• pp.147-154
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• 1992

This paper describes the design of implantable 8-channel telemetering system to get physiological signals. The internal circuits of this system are designed not only to achieve as small size and low power dissipation as possible, but also to enable continuous measurement of physiological signals. Its main functions are to enable continuous measurement of physiological signals and to accomplish on-off power switching of an implantable battery by receiving appropriate command signals from an external circuit. To integrate implantable biotelemetry system, we performed layout of internal system using Lambda based $2{\mu}m$ n-well design rules. This system, used together with appropriate sensors, is expected to be capable of measuring and transmitting such significant parameters as pressure, pH, and temperature.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.2
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• pp.333-338
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• 2008

In this paper, a new NMOS current-mirror type bridge rectifier for driving RFID chips, whose minimum input voltage required to obtain the effective DC output voltage is low enough and whose power dissipation can be reduced than that of conventional one, is proposed. The designed rectifier is able to supply high enough and well-rectified DC voltages to drive RFID transponder chips for the frequency range of 13.56 MHz HF(for ISO 18000-3), 915 MHz UHF(fur ISO 18000-6), and 2.45 GHz microwave(for ISO 18000-4). Output characteristics of the proposed rectifier are analyzed with the high frequency equivalent circuit. And the circuitry method for effective reducing of the gate leakage current due to the increasing of operating frequency is also proposed theoretically. Using this method, the power consumption of $100\;{\mu}W$ and the DC output voltage of 2.13V for 3V peak-to-peak input voltage and $45\;K{\Omega}$ load resistance are obtained. Compared to conventional one, the proposed rectifier operates in more stable and shows superior characteristics in UHF and microwave frequencies.

• Korean Journal of Applied Biomechanics
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• v.19 no.4
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• pp.697-705
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• 2009

The purpose of this study is to elucidate the possible cause of falling owing to mechanical energy in elderly women as compared to young women when performing the sit-to-walk movement. Two groups participated in this study: 10 elderly women and 10 young women. We used a ProReflex MCU camera (Qualisis, Sweden) and ground reaction force to evaluate the mechanical work. The muscle power (W) showed the same low negative work in both groups in the extension phase of the knee and hip joints while varying the angular velocity and net muscle moment of force. Elderly women, in particular, showed lower negative work. In mechanical work (J), the knee and hip joints of both groups showed the same amount of negative work in the extension phase. In the hip joint, elderly women showed lower negative work results in each phase. These result showed the possible reasons of falling for elderly women according to the weakness of the thigh muscle of the hip joint during the sit-to-walk movement.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.7
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• pp.1347-1353
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• 2015

We implemented a 10 Gb/s 4-channel vertical cavity surface emission lasers (VCSEL) driver array in a $0.13{\mu}m$ CMOS process technology. To enhance high current resolution, power dissipation, and chip space area, digital APC/AMC with time division sensing technology is primarily adopted. The measured -3 dB frequency bandwidth is 9.2 GHz; the small signal gain is 10.5 dB; the current resolution is 0.01 mA/step, suitable for the wavelength operation up to 10 Gb/s over a wide temperature range. The proposed APC and AMC demonstrate 5 to 20 mA of bias current control and 5 to 20 mA of modulation current control. The whole chip consumes 371 mW of low power under the maximum modulation and bias currents. The active chip size is $3.71{\times}1.3mm^2$.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.11-20
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• 1998

High-speed complex-number arithmetic units are essential to baseband signal processing of modern digital communication systems such as channel equalization, timing recovery, modulation and demodulation. In this paper, a new complex-number multiplication algorithm is proposed, which is based on redundant binary (RB) arithmetic combined with radix-4 Booth recoding scheme. The proposed algorithm reduces the number of partial product by one-half as compared with the conventional direct method using real-number multipliers and adders. It also leads to a highly parallel architecture and simplified circuit, resulting in high-speed operation and low power dissipation. To demonstrate the proposed algorithm, a prototype complex-number multiplier-accumulator (CMAC) core with 10-bit operands has been designed using 0.8-$\mu\textrm{m}$ N-Well CMOS technology. The designed CMAC core contains about 18,000 transistors on the area of about 1.60 ${\times}$ 1.93 $\textrm{mm}^2$. The functional and speed test results show that it can operate with 120-MHz clock at V$\sub$DD/=3.3-V, and its power consumption is given to about 63-mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.82-90
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• 2011

A novel class AB current subtracter(CS) and its application to Norton amplifier(NA) for low-power current-mode signal processing are designed. The CS is composed of a translinear cell, two current mirrors, and two common-emitter(CB) amplifiers. The principle of the current subtraction is that the difference of two input current applied translinear cell get from the current mirror, and then the current amplify through CB amplifier with ${\beta}$ times. The NA is consisted of the CS and wideband voltage buffer. The simulation results show that the CS has current input impedance of $20{\Omega}$, current gain of 50, and current input range of $i_{IN1}$ > $i_{IN2}{\geq}4I_B$. The NA has unit gain frequency of 312 MHz, transresistance of 130 dB, and power dissipation of 4mW at ${\pm}2.5V$ supply voltage.