• Laser Solutions
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• v.18 no.1
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• pp.1-6
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• 2015

High welding speed and narrow weld seam are favorable for welding of magnesium alloy. Magnesium alloy is recommended for the smart frame because it has several advantages such as low density, high thermal conductivity, EMI shielding capability and good cast ability. This study is for the assembly welding of the magnesium smart frame with high productivity, good performance and low cost. The window for battery on AZ91D frame produced by die-casting was prepared by CNC machining. Corresponding AZ31 blank of 0.2mm thickness was prepared by die-blanking cut. All system set was fixed at the stationary bed but the laser beam was manipulated by scanner up-to 1,000mm/s speed. The weld joint between AZ31 sheet and AZ91D frame was welded by fiber laser on 850~1,000W output power. The joint showed penetration enough but some humping bead. The distortion by the weld heat was almost free because of the quick dissipation of the heat by small beam size and fast welding. Consequently, the thinner magnesium foil was assembled successfully to the magnesium frame of mobile phone.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.55-68
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• 2001

This paper presents a new ALU architecture to minimize glitching power consumption which is appeared in the conventional one with P(carry propagation)/G(carry generation) blocks. In general, A lot of glitches generated once are propagating into the next stage of circuits to make unnecessary power dissipation. Therefore, a new ALU architecture which removes the glitches at the output of P/G blocks is presented in this paper. If a lot of glitches at the output of P/G blocks are removed, then the signal transitions caused by glitches are reduced in the sum generation block and hence power consumption is also reduced. A latch is inserted into the conventional P/G blocks to remove the glitches at the output of P/G blocks. Latch enable signal can make a role in eliminating a lot of glitches at the P/G's outputs by controlling output enable time. Experimental results from HSPICE simulations with implementing 16-b ALU show 28% reduction in glitching power consumption with negligible delay penalty.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.15-22
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• 2006

In this paper, 1.8V 8-bit 500MSPS Low-power CMOS Digital-to-Analog Converter(DAC) for UWB(Ultra Wide Band) Communication Systeme is proposed. The architecture of the DAC is based on a current steering 6+2 full matrix type which has low glitch and high linearity. In order to achieve a high speed and good performance, a current cell with a high output impedance and wide swing output range is designed. Further a thermometer decoder with same delay time and low-power switching decoder for high efficiency performance are proposed. The proposed DAC was implemented with TSMC 0.18um 1-poly 6-metal N-well CMOS technology. The measured SFDR was 49dB when the output frequency was 50MHz at 500MS/s sampling frequency. The measured INL and DNL were 0.9LSB and 0.3LSB respectively. The DAC power dissipation was 20mW and the effective chip area was $0.63mm^2$.

• Atmosphere
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• v.28 no.2
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• pp.223-232
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• 2018

The Global-Korean aviation Turbulence Guidance (G-KTG) system is developed using the operational Global Data Assimilation and Prediction System of Korea Meteorological Administration with 17-km horizontal grid spacing. The G-KTG system provides an integrated solution of various clear-air turbulence (CAT) diagnostics and mountain-wave induced turbulence (MWT) diagnostics for low [below 10 kft (3.05 km)], middle [10 kft (3.05 km) - 20 kft (6.10 km)], and upper [20 kft (6.10 km) - 50 kft (15.24 km)] levels. Individual CAT and MWT diagnostics in the G-KTG are converted to a 1/3 power of energy dissipation rate (EDR). 12-h forecast of the G-KTG is evaluated using 6-month period (2016.06~2016.11) of in-situ EDR observation data. The forecast skill is calculated by area under curve (AUC) where the curve is drawn by pairs of probabilities of detection of "yes" for moderate-or-greater-level turbulence events and "no" for null-level turbulence events. The AUCs of G-KTG for the upper, middle, and lower levels are 0.79, 0.69, and 0.63, respectively. Comparison of the upper-level G-KTG with the regional-KTG in East Asia reveals that the forecast skill of the G-KTG (AUC = 0.77) is similar to that of the regional-KTG (AUC = 0.79) using the Regional Data Assimilation and Prediction System with 12-km horizontal grid spacing.

• Journal of Aerospace System Engineering
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• v.14 no.3
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• pp.51-59
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• 2020

In the case of cubesat, a PCB-based deployable solar panel advantageous in terms of weight reduction and electrical circuit design is widely used considering the limited weight and volume of satellites. However, because of the low thermal conductivity of PCB, there is a limit relative to heat dissipation. In this paper, the thermal gap pad is applied to the contact between the PCB-based solar panel and the aluminum stiffener mounted on the outside of the panel. Thus, the heat transfer from the solar cell to the rear side of the panel is facilitated. It maximizes the heat dissipation performance while maintaining the merits of PCB panel, and thus, it is possible to improve the power generation efficiency from reducing the temperature of the solar cell. The effectiveness of the thermal design of the 6U cubesat's deployable solar panel using the thermal gap pad has been verified through on-orbit thermal analysis based on the results, compared with the conventional PCB-based solar panel.

• Journal of the Semiconductor & Display Technology
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• v.21 no.1
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• pp.148-154
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• 2022

As the 4th industrial age approaches, the demand for semiconductors is increasing enough to be used in all electronic devices. At the same time, semiconductor technology is also developing day by day, leading to ultraprecision and low power consumption. Semiconductors that keep getting smaller generate heat because the energy density increases, and the generated heat changes the shape of the semiconductor package, so it is important to manage. The temperature change is not only self-heating of the semiconductor package, but also heat generated by external damage. If the package is deformed, it is necessary to manage it because functional problems and performance degradation such as damage occur. The package burn in test in the post-process of semiconductor production is a process that tests the durability and function of the package in a high-temperature environment, and heat dissipation performance can be evaluated. In this paper, we intend to review a new material formulation that can improve the performance of the adapter, which is one of the parts of the test socket used in the burn-in test. It was confirmed what characteristics the basic base showed when polyamide, a high-molecular material, and alumina, which had high thermal conductivity, were mixed for each magnification. In this study, functional evaluation was also carried out by injecting an adapter, a part of the test socket, at the same time as the specimen was manufactured. Verification of stiffness such as tensile strength and flexural strength by mixing ratio, performance evaluation such as thermal conductivity, and manufacturing of a dummy device also confirmed warpage. As a result, it was confirmed that the thermal stability was excellent. Through this study, it is thought that it can be used as basic data for the development of materials for burn-in sockets in the future.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.7-13
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• 2009

This paper presents a multi-channel transceiver that achieves a data rate of 3.125Gb/s/ch. The LVDS is used because of its noise immunity and low power consumption. And a pre-emphasis circuit is also proposed to increase the transmitter speed. On the receiver side, a low-power CDR(clock and data recovery) using 1/4-rate clock based on dual-interpolator is proposed. The CDR generates needed additional clocks in each recovery part internally using only inverters. Therefore each part can be supplied with the same number of 1/4-rate clocks from a clock generator as in 1/2-rate clock method. Thus, the reduction of a clock frequency relaxes the speed limitation and lowers power dissipation. The prototype chip is comprised of two channels and was fabricated in a $0.18{\mu}m$ standard CMOS process. The output jitter of transmitter is loops, peak-to-peak(0.31UI) and the measured recovered clock jitter is 47.33ps, peak-to-peak which is equivalent to 3.7% of a clock period. The area of the chip is $3.5mm^2$ and the power consumption is about 119mW/ch.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.11-19
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• 1999

Fractal image compression algorithm has been studied mostly not in the view of hardware but software. However, a general processor by software can't decode fractal compressed images in real-time. Therefore, it is necessary that we develop a fast dedicated hardware. However, design examples of dedicated hardware are very rare. In this paper, we designed a quadtree fractal-based compressed image decoder which can decode $256{\times}256$ gray-scale images in real-time and used two power-down methods. The first is a hardware-optimized simple post-processing, whose role is to remove block effect appeared after reconstruction, and which is easier to be implemented in hardware than non-2' exponents weighted average method used in conventional software implementation, lessens costs, and accelerates post-processing speed by about 69%. Therefore, we can expect that the method dissipates low power and low energy. The second is to design a power dissipation in the multiplier can be reduced by about 28% with respect to a general array multiplier which is known efficient for low power design in the size of 8 bits or smaller. Using the above two power-down methods, we designed decoder's core block in 3.3V, 1 poly 3 metal, $0.6{\mu}m$ CMOS technology.

• Journal of Biomedical Engineering Research
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• v.28 no.3
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• pp.429-440
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• 2007

A coded excitation has been studied to improve the performance for ultrasound imaging in term of SNR, imaging frame rate, contrast to tissue ratio, and so forth. However, it requires a complicated arbitrary waveform transmitter for each active channel that is typically composed of a multi-bit Digital-to-Analog Converter (DAC) and a linear power amplifier (LPA). Not only does the LPA increase the cost and size of a transmitter block, but it consumes much power, increasing the system complexity further and causing a heating-up problem. This paper proposes an optimized 1.5bit fourth order sigma-delta modulation technique applicable to design an efficient arbitrary waveform generator with greatly reduced power dissipation and hardware. The proposed SDM can provide a required SQNR with a low over-sampling ratio of 4. To this end, the loop coefficients are optimized to minimize the quantization noise power in signal band while maintaining system stability. In addition, the decision level for the 1.5 bit quantizer is optimized for a given input waveform, which results in the SQNR improvement of more than 5dB. Computer simulation results show that the SQNR of a FM(frequency modulated) signal generated by using the proposed method is about 26dB, and the peak side-lobe level (PSL) of its compressed waveform on receive is -48dB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.9
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• pp.663-670
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• 2001

This paper proposes a new power reduction method for 2D FIR (Finite Impulse Response) filters. We exploited the spatial redundancy of image data in order to reduce power dissipation in multiplication of FIR filters. Since the higher bits of input pixels are hardly changed, the redundant multiplication of higher bits is avoided by separating multiplication into higher and lower parts. The calculated values of higher bits are stored in memory cells, cache such that they can be reused when a cache hit occurs. Therefore, we can reduce power in 2D FIR Filter modules about 15% by using the proposed separated multiplication Technique (SMT).