• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.4
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• pp.571-578
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• 2023

In this paper, we propose a low EMI data transmitter employing a delay-locked loop for vehicles. For the low EMI characteristic, the transmitter has been designed to have low slew rate and employs the delay-locked loop to correct the amount of change in the slew rate due to process variations. According to simulation results, the proposed transmitter which the delay-locked loop has smaller slew rate change as compared to the conventional transmitter. The proposed circuit has been designed with a 65nm process technology and the data rate is 20Mbps with a supply voltage of 1.1V. As compared to a conventional transmitter, the proposed transmitter shows that variations of the slew rate become 53.6% lower in a fast condition and 13.07% lower in a slow condition.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.9
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• pp.6247-6253
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• 2015

This paper presents the transient-response improved LDO regulator based on parallel error amplifiers. The proposed LDO regulator consists of an error amplifier (E/A1) which has a high gain and narrow bandwidth and a second amplifier (E/A2) which has low gain and wide bandwidth. These amplifiers are in parallel structure. Also, to improve the transient-response properties and slew-rate, some circuit block is added. Using pole-splitting technique, an external capacitor is reduced in a small on-chip size which is suitable for mobile devices. The proposed LDO has been designed and simulated using a Megna/Hynix $0.18{\mu}m$ CMOS parameters. Chip layout size is $500{\mu}m{\times}150{\mu}m$. Simulation results show 2.5 V output voltage and 100 mA load current in an input condition of 2.7 V ~ 3.3 V. Regulation Characteristic presents voltage variation of 26.1 mV and settling time of 510 ns from 100mA to 0 mA. Also, the proposed circuit has been shown voltage variation of 42.8 mV and settling time of 408 ns from 0 mA to 100 mA.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.5
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• pp.587-592
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• 2018

Because the brightness of an AMOLED is determined by the flowing current, each pixel of AMOLED operates via A current driving method. Therefore, it is necessary to supply power to adjust the amount of current according to THE user's requirement for AMOLED driving. In this study, an IP driver block was designed and a simulation was conducted for an AMOLED display, which supplies power as selected by users. The IP driver design focused on regulating the output power due to the OLED characteristics for the diode electric current according to the voltage to be activated by pulse-skipping mode (PSM) under low loads, and 1.5 MHz pulse-width modulation (PWM) for medium/high loads. The IP driver was designed to eliminate the ringing effects appearing from the dis-continue mode (DCM) of the step-up converter. The ringing effects destroy the power switch within the IC, or increase the EMI to the surrounding elements. The IP driver design minimized this through a ringing killer circuit. Mobile applications were considered to enable true shut-down capability by designing the standby current to fall below $1{\mu}A$ to disable it. The driver proposed in this paper can be applied effectively to the same system as the AMOLED display dual power management circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.673-684
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• 2003

A degenerated differential pair has been widely used as a standard topology for digitally programmable CMOS VGAs. A variable degeneration resistor has been implemented using a resistor string or R-2R ladder with MOSFET switches. However, in the VGAs using these conventional methods, low-voltage and high-speed operation is very hard to achieve due to the dc voltage drop over the degeneration resistor. To overcome this problem a new variable degeneration resistor is proposed where the dc voltage drop is almost removed. Using the proposed gain control scheme, a low-voltage and high-speed CMOS VGA is designed. HSPICE simulation results using a 0.25${\mu}{\textrm}{m}$ CMOS process parameters show that the designed VGA provides a 3dB bandwidth of 360MHz and a 80dB gain control range in 2dB step. Gain errors are less than 0.4dB at 200MHz and less than l.4dB at 300MHz. The designed circuit consumes 10.8mA from a 2.5V supply and its die area is 1190${\mu}{\textrm}{m}$${\times}$360${\mu}{\textrm}{m}$.

• ETRI Journal
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• v.38 no.4
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• pp.685-694
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• 2016

A surface micromachined piezoresistive pressure sensor with a novel internal substrate vacuum cavity was developed. The proposed internal substrate vacuum cavity is formed by selectively etching the silicon substrate under the sensing diaphragm. For the proposed cavity, a new fabrication process including a cavity side-wall formation, dry isotropic cavity etching, and cavity vacuum sealing was developed that is fully CMOS-compatible, low in cost, and reliable. The sensitivity of the fabricated pressure sensors is 2.80 mV/V/bar and 3.46 mV/V/bar for a rectangular and circular diaphragm, respectively, and the linearity is 0.39% and 0.16% for these two diaphragms. The temperature coefficient of the resistances of the polysilicon piezoresistor is 0.003% to 0.005% per degree of Celsius according to the sensor design. The temperature coefficient of the offset voltage at 1 atm is 0.0019 mV and 0.0051 mV per degree of Celsius for a rectangular and circular diaphragm, respectively. The measurement results demonstrate the feasibility of the proposed pressure sensor as a highly sensitive circuit-integrated pressure sensor.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.8
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• pp.1215-1221
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• 2017

Parametric array transducers are used for highly directional speaker in an air environments. Piezoelectric micromachined ultrasonic transducers for parametric array transducers need DC-biased voltage driving signals in order to get high-directional quality-sound features. The existing power amplifier such as class A amplifiers has low efficiency and require large volume heatsinks. To overcome the above-mentioned disadvantages of the conventional amplifier, this paper proposes a new power amplifier system. The proposed power amplifier system ensures high linearity of output characteristic by utilizing the push-pull class B type amplifier. Furthermore, the proposed power amplifier system gets high efficiency because it contains the DC-DC converter-type power supply which can perform energy recovery and envelope tracking function. Also the paper suggests the detailed circuit topology. Its characteristics are verified by the detailed experimental results.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.1254-1257
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• 2004

This paper presents a built-in current sensor(BICS) that can detect defects in CMOS integrated circuits through current testing technique - Iddq test. Current test has recently been known to a complementary testing method because traditional voltage test cannot cover all kinds of bridging defects. So BICS is widely used for current testing. but there are some critical issues - a performance degradation, low speed test, area overhead, etc. The proposed BICS has a two operating mode- normal mode and test mode. Those methods minimize the performance degradation in normal mode. We also used a current-mode differential amplifier that has a input as a current, so we can realize higher speed current testing. Furthermore, only using 10 MOSFETS and 3 inverters, area overhead can be reduced by 6.9%. The circuit is verified by HSPICE simulation with 0.25 urn CMOS process parameter.

• Journal of IKEEE
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• v.17 no.4
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• pp.544-549
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• 2013

This paper describes a modified binary phase detector (Bang-Bang phase detector - BBPD) for jitter reduction in clock and data recovery (CDR) circuits. The proposed PD reduces ripples in the VCO control voltage resulting in reduced jitter for CDR circuits. A 2.5 Gbps CDR circuit with a proposed BBPD has been designed and verified using Dongbu $0.13{\mu}m$ CMOS technology. Simulation shows the CDR with proposed PD recovers data with peak-to-peak jitter of 10.96ps, rms jitter of 0.86ps, and consumes 16.9mW.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.167-174
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• 2012

In this paper a ultrasonic oil level meter for measuring oil levels of vehicle transmissions is designed and its effectiveness is shown by experiments. On a FPGA(Field Programmable Gate Array) project IDE(Integrated Development Environment), all digital circuits for the meter is designed using a FPGA, which enables simplicity and high performance of the meter as well as short developing time. Also, power supplying circuit and analog circuits to process low voltage ultrasonic echo signal are designed and simulated. Under experiments, the designed level meter is verified to provide accuracy to within 1mm.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.648-653
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• 1998

The conventional three-phase rectifier with bulky LC output filter has been widely used in the industry because of its distinctive advantages over the active power factor correction rectifier such as simple circuit, high reliability, and low cost. Over than 0.9 power factor can be achieved, which is acceptable in most of industry applications. This rectifier, however, is not easy to use for high power density applications since the LC filter is bulky and heavy. To solve this problem, a new simple rectifier is presented in this paper. By eliminating the bulky LC filter from the conventional diode rectifier without losing most of the advantages of the conventional rectifier, very high power density power conversion with high power factor can be achieved. Operation principle and design considerations are illustrated and verified by Pspice simulation and experimental results from a prototype of 3.3 kW rectifier followed by 100KHz zero voltage switching full bridge PWM converter