• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.647-650
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• 2005

In this paper, a low voltage SRAM using double boosting scheme is described. A low supply voltage deteriorates the static noise margin (SNM) and the cell read-out current. For read/write operation, a selected word line and cell VDD bias are boosted in a different level using double boosting scheme. This increases not only the static noise margin but also the cell readout current at a low supply voltage. A low voltage SRAM with 32K ${\times}$ 8bit implemented in a 0.18um CMOS technology shows an access time of 26.1ns at 0.8V supply voltage.

• The Magazine of the IEIE
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• v.37 no.8
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• pp.50-59
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• 2010

$0.18-{\mu}m$ high voltage technology 13.5V high voltage well-based symmetric EDMOS isolated by MTI was designed and fabricated. Using calibrated process and device model parameters, the characteristics of the symmetric and asymmetric EDMOS have been simulated. The asymmetric EDMOS has higher performance, better $R_{sp}$ / BVDSS figure-of-merit, short-channel immunity and smaller pitch size than the symmetric EDMOS. The asymmetric EDMOST is a good candidate for low-power and smaller source driver chips. The low voltage logic well-based EDMOS process has advantages over high voltage well-based EDMOS in process cost by eliminating the process steps of high-voltage well/drift implant, high-temperature long-time thermal steps, etc. The specific on-resistance of our well-designed logic well-based EDMOSTs is compatible with the smallest one published. TCAD simulation and measurement results show that the improved logic well-based nEDMOS has better electrical characteristics than those of the conventional one. The improved EDMOS proposed in this paper is an excellent candidate to be integrated with low voltage logic devices for high-performance low-power low-cost chips.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.923-926
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• 2003

This paper presents a novel low voltage reference circuit under the MOS threshold voltage(V$_{th}$) in standard CMOS process. It is based on the weighted difference of the gate-source voltages of an NMOS and a PMOS operating in saturation region. The voltage reference is designed for low power OLED driver ICs. The proposed circuit is designed using 0.35${\mu}{\textrm}{m}$ CMOS technology. The minimum supply voltage is 2V, and the typical temperature coefficient is 99.6ppm/ C.C.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.3
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• pp.252-256
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• 2009

We have developed low driving voltage white organic light emitting diode with a new electron transport material, triphenylphosphine oxide ($Ph_{3}PO$). The white light emission was realized with a rubrene yellow dopant and blue-emitting DPVBi layer. The new electron transport layer results in a very high current density at low voltage, resulting in a reduction of driving voltage. The device with a new electron transport layer shows a brightness of $1150\;cd/m^2$ at a low driving voltage of 4.3 V.

• Proceedings of the KIEE Conference
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• 2002.11d
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• pp.3-11
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• 2002

This paper presents the trend of low voltage and high current technology for DC-DC converters. It can be said that the output voltage of the on-board power supply has been rapidly moving forward a low voltage in proportion to the minuteness of the semiconductors. As for as its speed is concerned, the change of the market situation seems to be faster than that of R&D for the low voltage and high current products put out by power supply manufacturers. Here, the present situation and the trend of non-isolated type step-down DC-DC converter and isolated type DC-DC converter called "Brick" will be taken up mainly from the fellowing point of view. -low voltage and high current keeping up with the current demand for the latest telecommunication networks and broadband. -build-up of the total solution for dispersion system power supply. In this paper, an explanation is given to mainly concerning to the newest products in the supplier's position.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.471-475
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• 2010

This paper presents a frequency synthesizer using low voltage active inductor VCO(Voltage Controlled Oscillator). The low voltage active inductor VCO with feedback resistor increases its equivalent inductance and the quality-factor(Q). Under certain conditions, the low voltage active inductor with feedback resistor generates a negative resistance at the input. In this paper, the conditions for negative resistance are obtained by small signal analysis. The designed low voltage active inductor VCO covers a frequency band between 1059MHz and 1223MHz. The measured phase noise at 1.178GHz is -81.8dBc/Hz at 1MHz offset.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.10
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• pp.708-711
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• 2000

Sensorless PMSM is much studied for the industrial applications and home appliances because a mechanical sensor reduce reliability and increase cost. Most of sensorless algorithms are based on motor equations, and so the magnitude of phase voltage and current should be exactly obtained. However, the inverter output voltage applied to PMSM has relatively large error in the low speed range, and a relatively poor response is shown in the low speed range. This paper investigates the improved performance of sensorless PMSM in the low speed range. This paper proposes the error reduction of inverter output voltage which is realized through the variable link voltage. The proposed algorithm is verified through simulation and experiment.

• Journal of Advanced Marine Engineering and Technology
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• v.23 no.2
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• pp.159-167
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• 1999

This paper presents a new transient voltage blocking device(TOBD)which low power and high frequency bandwidth to protect info-communication facilities from transient voltages. Conventional protection devices have some problems such as low frequency bandwidth low ener-gy capacity and high remnant voltage. in order to improve these limitations a hybrid type TOBD which consists of a gas tube avalanche diodes and junction type field effect transistor (JFETs) is developed. The TOBD differs from the conventional protection devices in configuration and JFETs are used as an active non-linear element and a high speed switching diode with low capacitance limited high current. Therefore the avalanche diode with low energy capacity are protected from the high current and the TOBD has a very small input capacitance. From the performance test using combination surge generator which can produce $1.2/50{\mu}m$ 4.2 kV/max, $8/20{\mu}m$ 2.1 kAmax it is confirmed that the proposed TOBD has an excellent protection per-formance in tight clamping voltage and limiting current characteristics.

• Journal of Power Electronics
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• v.14 no.3
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• pp.531-540
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• 2014

A novel carrier-based PWM (CBPWM) strategy of a three-level NPC converter is proposed in this paper. The novel strategy can eliminate the low-frequency neutral point (NP) voltage oscillation under the entire modulation index and full power factor. The basic principle of the novel strategy is introduced. The internal modulation wave relationship between the novel CBPWM strategy and traditional SPWM strategy is also studied. All 64 modulation wave solutions of the CBPWM strategy are derived. Furthermore, the proposed CBPWM strategy is compared with traditional SPWM strategy regarding the output phase voltage THD characteristics, DC voltage utilization ratio, and device switching losses. Comparison results show that the proposed strategy does not cause NP voltage oscillation. As a result, no low-frequency harmonics occur on output line-to-line voltage and phase current. The novel strategy also has higher DC voltage utilization ratio (15.47% higher than that of SPWM strategy), whereas it causes larger device switching losses (4/3 times of SPWM strategy). The effectiveness of the proposed modulation strategy is verified by simulation and experiment results.

• Journal of Power Electronics
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• v.18 no.1
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• pp.11-22
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• 2018

This paper presents a single switch, high step-up, non-isolated dc-dc converter suitable for renewable energy applications. The proposed converter is composed of a coupled inductor, a passive clamp circuit, a switched capacitor and voltage lift circuits. The passive clamp recovers the leakage inductance energy of the coupled inductor and limits the voltage spike on the switch. The configuration of the passive clamp and switched capacitor circuit increases the voltage gain. A wide continuous conduction mode (CCM) operation range, a low turn ratio for the coupled inductor, low voltage stress on the switch, switch turn on under almost zero current switching (ZCS), low voltage stress on the diodes, leakage inductance energy recovery, high efficiency and a high voltage gain without a large duty cycle are the benefits of this converter. The steady state operation of the converter in the continuous conduction mode (CCM) and discontinuous conduction mode (DCM) is discussed and analyzed. A 200W prototype converter with a 28V input and a 380V output voltage is implemented and tested to verify the theoretical analysis.