• Journal of the Institute of Convergence Signal Processing
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• v.10 no.3
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• pp.158-163
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• 2009

LMS(Least Mean Square) algorithm requires simple equation and is used widely because of the low complexity. If the convergence speed increase, LMS algorithm has a divergence in case of sharp environment changes. And if a stability increase, the convergence speed becomes slow. This algorithm based on a trade off between fast convergence and system stability. To improve this problem, VSSLMS (Variable Step Size LMS) algorithm was developed. The VSSLMS algorithm improved the convergence speed and performance as adjusting step size using error signal. In this paper, I-VSSLMS algorithm is proposed tor improve the performance of adaptive noise canceller in real-time environments. The proposed algorithm is applied to adaptive noise canceller using TMS320C6713 DSP board and we did simulation by real time. Then we compared performance of each algorithm and demonstrated that proposed algorithm has superior performance.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.1
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• pp.9-14
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• 2019

A small millimeter-wave tracking radar is a pulse-based radar that searches, detects, and tracks a target in real time through a TWS (Track While Scan) method for a traps target on the sea with a large RCS running at low speed. It is necessary to develop a board equipped with a high-speed CPU to acquire and track target information through LPRF, DBS, and HRR signal processing techniques for a trap target operating various kinds of dexterous objects such as chaff and decoy, We designed a signal processor structure including DFT (Discrete Fourier Transform) module design that can perform real - time FFT operation using FPGA (Field Programmable Gate Array) and verified the signal processor implemented through performance test.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.2
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• pp.202-208
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• 2001

A Switched Reluctance Motor(SRM) has double salient poles structure and the phase windings are wound in stator. SRM hase more simple structure that of other motor, thus manufacture cost is low, mechanically strong, reliable to a poor environment such as high temperature, and maintenance cost is low because of brushless. SRM needs position detector to get rotator position information for phase excitation and tachometer or encoder for constant speed operation. But, this paper doesn\`s use an encoder of high cost for velocity measurement of rotator. Instead of it, the algorithm for position detection and velocity estimation from simple slotted disk has been proposed and developed. To implement variable speed digital control system with velocity estimation algorithm, the TMS320F240-20MIPS fixed point arithmetic processor of TI corporation is used. The experimental results of the developing system are enable to control speed with wide range, not only single pulse, hard chopping mode and soft chopping, ut also variable speed control, and advance angle control.

• Proceedings of the KIEE Conference
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• 1991.11a
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• pp.353-356
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• 1991

This paper proposes a robust direct adaptive control system implementation using a 80286 microprocessor-based system for controlling the speed of a DC servo motor. In this paper, assuming that the unmodeled dynamics of the plant are sufficiently small in the low-frequency range, the plant as linear time-invariant system is the second relative degree, we construct the direct adaptive control system with the algorithm considering plant unmodeled dynamics and execute the experiment, and compare the characteristics with those of PI algorithm's. It shows that an easy implementation of the built controller is due to the usage of software for the algorithm.

• Journal of Korean Society of Transportation
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• v.12 no.1
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• pp.97-116
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• 1994

Today advanced traffic management systems are required because of a high increase in traffic demand. Accordingly, the objective of this study is to take advantage of image processing systems and present image processing methods available for collection of the data on traffic characteristics, and then to investigate the possibility of traffic flow analysis by means of comparison and analysis of measured traffic flow. Data were collected at two places of Daegu city and Kyongbu expressway by using VTR. Rear view (down stream) and frontal view (up stream) methods were employed to compare and analyze traffic characteristics including traffic volume, speed, time-headway, time-occupancy, and vehicle-length, by analysis of measured traffic flow and image processing respectively. Judging from the results obtained by this study, image processing techniques are sufficient for the analysis of traffic volume, but a frame grabber equipped with high speed processor is necessary as well, with low level system judged to be sufficient for traffic volume analysis.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.3C
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• pp.175-182
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• 2011

This paper presents a novel eight-parallel 128/256-point mixed-radix multi-path delay commutator (MRMDC) FFT/IFFT processor for orthogonal frequency-division multiplexing (OFDM) systems. The proposed FFT architecture can provide a high throughput rate and low hardware complexity by using an eight-parallel data-path scheme, a modified mixed-radix multi-path delay commutator structure and an efficient scheduling scheme of complex multiplications. The efficient scheduling scheme can reduce the number of complex multipliers at the second stage from 88 to 40. The proposed FFT/IFFT processor has been designed and implemented with the 90nm CMOS technology. The proposed eight-parallel FFT/IFFT processor can provide a throughput rate of up to 27.5Gsample/s at 430MHz.

• Proceedings of the KSR Conference
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• 2011.10a
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• pp.1838-1844
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• 2011

In this paper, the propulsion control of a high-speed maglev train is studied. Electromagnetic suspension is used to levitate the vehicle, and linear synchronous motors (LSM) are used for propulsion. In general, a low-speed maglev train uses a linear induction motor (LIM) for propulsion that is operated under 300[km/h] due to the power-collecting and end-effect problem of LIM. In case of the high-speed maglev train over 500[km/h], a linear synchronous motor (LSM) is more suitable than LIM because of a high-efficiency and high-output properties. An optical barcode positioning system is used to obtain the absolute position of the vehicle due to its wide working distance and ease of installation. However, because the vehicle is working completely contactless, the position measured on the vehicle has to be transmitted to the ground for propulsion control via wireless communication. For this purpose, Bluetooth is used and communication hardware is designed. A propulsion controller using a digital signal processor (DSP) in the ground receives the delayed position information, calculates the required currents, and controls the stator currents through inverters. The performance of the implemented propulsion control is analyzed with a small maglev train which was manufactured for experiments, and the applicability of the high-speed maglev train will be explored.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.267-269
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• 2007

PLL(Phase Locked Loop) are widely used circuit technique in modern electronic systems. In this paper, We propose the low voltage and high speed PLL. We design the PFD(Phase Frequency Detector) by using TSPC (True Single Phase Clock) circuit to improve the performance and solve the dead-zone problem. We use CP(Charge Pump} and LP(Loop filter) for Negative feedback and current reusing in order to solve current mismatch and switch mismatch problem. The VCO(Voltage controlled Oscillator) with 5-stage differential ring oscillator is used to exact output frequency. The divider is implemented by using D-type flip flops asynchronous dividing. The frequency divider has a constant division ratio 32. The frequency range of VCO has from 200MHz to 1.1GHz and have 1.7GHz/v of voltage gain. The proposed PLL is designed by using 0.18um CMOS processor with 1.8V supply voltage. Oscillator's input frequency is 25MHz, VCO output frequency is 800MHz and lock time is 5us. It is evaluated by using cadence spectra RF tools.

• Journal of IKEEE
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• v.21 no.3
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• pp.260-263
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• 2017

Based on several CPU cores, an SoC including ADCs, DC-DC converter and 2M-byte SRAM is proposed in this paper. The CPU core consists of a 12-bit MENSA, a 32-bit Symmetric multi-core processor, as well as 16-bit CDSP. To eliminate the external SDRAM memory, internal 2M-byte SRAM is implemented. Because the SRAM normally occupies huge area, the parasitic components reduce the speed of SoC. In this work, the SRAM blocks are divided into small pieces to reduce the parasitic components. The proposed SoC is developed in a standard 55nm CMOS process and the speed of SoC is 200MHz.

• Journal of Institute of Control, Robotics and Systems
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• v.8 no.12
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• pp.1036-1040
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• 2002

To process data of digital linescan camera, the frame grabber is essential to handle the data in low-level and in high speed more than 30 MHz stably. Traditional approaches to the development of hardware in vision system for the special purpose are mai y based on PC system, and are expensive and gigantic. Therefore, there are many difficulties in applying those in the field. So we investigate, in this paper, the implementation of FPGA for real-time processing of digital linescan camera. The system is not based on PC, but electronic device such as micropncessor. So it is expected that the use of FPGAs for low-level processing represents a fast, stable and inexpensive system. The experiments are carried out on the web guiding system in order to show the efficiency of the new image processor.