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http://dx.doi.org/10.7840/KICS.2011.36C.3.175

High Speed 8-Parallel Fft/ifft Processor using Efficient Pipeline Architecture and Scheduling Scheme  

Kim, Eun-Ji (아주대학교 정보통신대학 전자공학부)
SunWoo, Myung-Hoon (아주대학교 정보통신대학 전자공학부)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.36, no.3C, 2011 , pp. 175-182 More about this Journal
Abstract
This paper presents a novel eight-parallel 128/256-point mixed-radix multi-path delay commutator (MRMDC) FFT/IFFT processor for orthogonal frequency-division multiplexing (OFDM) systems. The proposed FFT architecture can provide a high throughput rate and low hardware complexity by using an eight-parallel data-path scheme, a modified mixed-radix multi-path delay commutator structure and an efficient scheduling scheme of complex multiplications. The efficient scheduling scheme can reduce the number of complex multipliers at the second stage from 88 to 40. The proposed FFT/IFFT processor has been designed and implemented with the 90nm CMOS technology. The proposed eight-parallel FFT/IFFT processor can provide a throughput rate of up to 27.5Gsample/s at 430MHz.
Keywords
O-OFDM; UWB; FFT; Mixed-radix; MDC;
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