• The Transactions of the Korean Institute of Electrical Engineers P
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• v.66 no.4
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• pp.247-251
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• 2017

This paper proposes a low power transmission technique for single-carrier modulation with frequency domain equalization. As time domain signals and frequency domain signals have unique corresponding functions, inserting zeros after each symbol causes a repetition in other domain, so maximal ratio combining technique using repetitive transmission can be applied in the frequency domain. In this paper, we configure transmit signals to insert zeros after each symbols for single-carrier modulation with frequency domain equalization and maximal ratio receive combining block in the receiver structures, propose a structure for transmitter and receiver and show that its performance is better than the traditional algorithm by simulations.

• ETRI Journal
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• v.30 no.4
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• pp.612-614
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• 2008

A novel linear switched termination active cross-coupled low-voltage differential signaling (LVDS) transceiver operating at 1.5 GHz clock frequency is presented. On the transmitter side, an active cross-coupled linear output driver and a switched termination scheme are applied to achieve high speed with low current. On the receiver side, a shared pre-amplifier scheme is employed to reduce power consumption. The proposed LVDS transceiver implemented in an 80 nm CMOS process is successfully demonstrated to provide a data rate of 6 Gbps/pin, an output data window of 147 ps peak-to-peak, and a data swing of 196 mV. The power consumption is measured to be 4.2 mW/pin at 1.2 V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.8
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• pp.610-618
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• 2017

This paper presents a 868/915 MHz CMOS RF transceiver for the ZigBee application. Using a switchless matching network, the off chip switch is removed to achieve the low cost RF transceiver, and by the elimination of the switch's insertion loss we can achieve the benefits for the RF receiver's noise figure and transmitter's power efficiency at the given output power. The receiver is composed of low-noise amplifier, mixer, and baseband analog(BBA) circuit. The transmitter is composed of BBA, mixer, and driver amplifier. And, the integer N type frequency synthesizer is designed. The proposed ZigBee RF full transceiver is implemented on the $0.18{\mu}m$ CMOS technology. Measurement results show that the maximum gain and the noise figure of the receiver are 97.6 dB and 6.8 dB, respectively. The receiver consumes 32 mA in the receiver mode and the transmitter 33 mA in the transmission mode.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.7-13
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• 2009

This paper presents a multi-channel transceiver that achieves a data rate of 3.125Gb/s/ch. The LVDS is used because of its noise immunity and low power consumption. And a pre-emphasis circuit is also proposed to increase the transmitter speed. On the receiver side, a low-power CDR(clock and data recovery) using 1/4-rate clock based on dual-interpolator is proposed. The CDR generates needed additional clocks in each recovery part internally using only inverters. Therefore each part can be supplied with the same number of 1/4-rate clocks from a clock generator as in 1/2-rate clock method. Thus, the reduction of a clock frequency relaxes the speed limitation and lowers power dissipation. The prototype chip is comprised of two channels and was fabricated in a $0.18{\mu}m$ standard CMOS process. The output jitter of transmitter is loops, peak-to-peak(0.31UI) and the measured recovered clock jitter is 47.33ps, peak-to-peak which is equivalent to 3.7% of a clock period. The area of the chip is $3.5mm^2$ and the power consumption is about 119mW/ch.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.110-116
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• 2016

This paper describes 1.2-V 5-Gb/s scalable low voltage signaling(SLVS) differential transmitter(TX) with a digital impedance calibration and equalizer. The proposed transmitter consists of a phase-locked loop(PLL) with 4-phase output clock, a 4-to-1 serializer, a regulator, an output driver, and an equalizer driver for improvement of the signal integrity. A pseudo random bit sequence generator is implemented for a built-in self-test. The proposed SLVS transmitter provides the output differential swing level from 80mV to 500mV. The proposed SLVS transmitter is implemented by using a 65-nm CMOS with a 1.2-V supply. The measured peak-to-peak time jitter of the implemented SLVS TX is about 46.67 ps at the data rate of 5Gb/s. Its power consumption is 1.88 mW/Gb/s.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.40 no.5
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• pp.461-466
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• 2012

This paper describes the development and test result of X-band Transmitter flight model(FM) of STSAT-3 by satellite research center(SaTReC), KAIST. The communication sub-system of STSAT-3 is consist of two different frequency band channels. S-band frequency is used for Telemetry & Command, and X-band frequency is used for mission data. Payload observations data in Mass Memory Unit (MMU) is modulated by QPSK modulator in X-band Transmitter, and then QPSK modulation signal is transmitted to antenna through transfer switch. In this Paper, we described the results of modulation, low-pass filter design, power amp development, and switch test. The FM XTU is delivered Spacecraft Assembly, Integration and Test(AIT) level through the completion of functional Test and environmental(vibration, thermal vacuum) Test successfully.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.2
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• pp.361-370
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• 1997

In this paper, we designed POCSAG Signal Decoder to improve operating time in pager. We showed POCSAG Signal Pattern sent by transmitter and operation of this decoder. We also showed that the Pager using this decoder was equipped with Wide Area Signal Detection and designed the hardware which realizes this operation and implemented it with ASIC chip. As we inspected the function of the ASIC chip and tested the performance, we could find that the chip operated in low voltage and that power dissipation was low.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.357-360
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• 2013

A 1.8V 2-Gb/s scalable low voltage signaling (SLVS) transmitter (TX) is designed for mobile applications requiring high speed and low power consumption. It consists of 4-lane TX for data transmission, 1-lane TX for a source synchronous clocking, and a 8-phase clock generator. The proposed SLVS TX has the scaling voltage swing from 50 mV to 650 mV and supports a high speed (HS) mode and a low power (LP) mode. An output impedance calibration scheme for the SVLS TX is proposed to improve the signal integrity. The proposed SLVS TX is implemented by using a $0.18-{\mu}m$ 1-poly 6-metal CMOS with a 1.8V supply. The simulated data jitter of the implemented SLVS TX is about 8.04 ps at the data rate of 2-Gbps. The area and power consumption of the 1-lane of the proposed SLVS TX are $422{\times}474{\mu}m^2$ and 5.35 mW/Gb/s, respectively.

• The Journal of the Korea Contents Association
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• v.10 no.12
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• pp.10-17
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• 2010

In this paper, we design digital D-PHY link chip controling DSI (Display Serial Interface) that meets MIPI (Mobile Industry Processor Interface) standard. The D-PHY supports a high-speed (HS) mode for fast data traffic and a low-power (LP) mode for control transactions. For low power consumption, the unit blocks in digital D-PHY are optionally switched using the clock gating technique. The proposed low power digital D-PHY is simulated and compared with conven tional one about power consumption on each transaction mode. As a result, power consumptions of TX, RX, and total in HS mode decrease 74%, 31%, and 50%, respectively. In LP mode, power reduction rates of TX, RX, and total are 79%, 40%, and 51.5%, separately. We implemented the low power MIPI D-PHY digital chip using $0.13-{\mu}m$ CMOS process under 1.2V supply.

• Journal of Advanced Navigation Technology
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• v.24 no.6
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• pp.566-572
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• 2020

In a wireless power transmitter, the characteristics and effects of wireless power transmission between two induction coils are investigated, and a power converter circuit and a battery charger/discharger circuit using wireless power transmission technology are proposed. The advantage of wireless power transmitters and wireless chargers is that, instead of the existing plug-in-mounted wired charger (OBC; on-board charger), the user can wirelessly charge the battery without connecting the power source when charging power to the battery. There is. In addition, the advantage of wireless charging can bring about an energy efficiency improvement effect by using the secondary side rectifier circuit and the receiving coil, but the large-capacity long-distance wireless charging method has a limitation on the transmission distance, so many studies are currently being conducted. The purpose of the study is to study the transmitter circuit and receiver circuit of a wireless power transmission device using a primary coil, a secondary coil, and a half bridge series resonance converter, which can transmit power of a non-contact type power transmitter. As a result, a new topology was applied to improve the power transmission distance of the wireless charging system, and through an experiment according to each distance, the maximum efficiency (95.8%) was confirmed at an output of 3 kW at an 8 cm transmission distance.