• Journal of IKEEE
• /
• v.11 no.1 s.20
• /
• pp.69-76
• /
• 2007

This paper presents the design of LVDS (Low-Voltage-Differential-Signaling) transmitter for Gb/s-per-pin operation. The proposed LVDS transmitter is designed using BiCMOS technology, which can be compatible with CMOS technology. To reduce chip area and enhance the robustness of LVDS transmitter, the MOS switches of transmitter are replaced with lateral bipolar transistor. The common emitter current gain($\beta$) of designed bipolar transistor is 20 and the cell size of LVDS transmitter is $0.01mm^2$. Also the proposed LVDS driver is operated at 1.8V and the maximum data rate is 2.8Gb/s approximately In addition, a novel ESD protection circuit is designed to protect the ESD phenomenon. This structure has low latch-up phenomenon by using turn on/off character of P-channel MOSFET and low triggering voltage by N-channel MOSFET in the SCR structure. The triggering voltage and holding voltage are simulated to 2.2V, 1.1V respectively.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.4
• /
• pp.415-424
• /
• 2016

This paper describes a high data rate proximity transmitter design for high resolution smartphone-mirrored display applications. A 2 Gb/s transmitter is designed with a low transmission power of -70 dBm/MHz and a wide bandwidth of nearly 3 GHz. A digital pre-correction method is employed in the transmitter to mitigate the inter-symbol interference problem. A carrier-based digital pulse shaping and a reconfigurable digital envelope generation methods are employed for robust operation by utilizing 20 phases from a 2 GHz phase-locked loop. A 6.5-9.5 GHz transmitter implemented in 65 nm CMOS achieves the maximum data rate of 2 Gb/s, consuming only 7.6 mW from a 1 V supply.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.9C
• /
• pp.871-878
• /
• 2002

The cartesian loop chip which is one of key devices in narrow-band Walky-Talky transmitter using RZ-SSB modulation method was designed and implemented with 0.35 ㎛ CMOS technology. The reduced size and low cost of transmitter were available by the use of direct-conversion and cartesian loop chip, which improved the power efficiency and linearity of transmitter. In addition, low power operation was possible through CMOS technology. The performance test results of transmitter showed -23㏈c improvement of IMD and -30㏈c below suppression of SSB characteristic in the operation of cartesian loop chip (closed-loop). At that time, the transmitting power was about 37㏈m (5W). The main parameters to improve the transmitting characteristic and to compensate the distortion in feed back loop such as DC-offset, loop gain and phase value are interfaced with notebook PC to be controlled with S/W.

• Journal of Sensor Science and Technology
• /
• v.19 no.6
• /
• pp.469-474
• /
• 2010

This paper presents a 10Gbps CMOS parallel-to-serial converter for transmission of sensor data. A low-noise clock multiplying unit(CMU) and a multiplexer with controllable data sequence are proposed. The transmitter was fabricated in 0.13 um CMOS process and the measured total output jitter was less than 0.1 UIpp(unit-interval, peak-to-peak) over 20 kHz to 80 MHz bandwidth. The jitter of the CMU output only was measured as 0.2 ps,rms. The transmitter dissipates less than 200 mW from 1.5 V/2.5 V power supplies.

• The Transactions of the Korean Institute of Electrical Engineers A
• /
• v.48 no.3
• /
• pp.330-335
• /
• 1999

Recently, there a lot of activities on the researches that implement many kinds of control system using power lines. To implement that, it is desirable to use hybrid PSK model because it takes advantage of PSK and DPSK which has a low-bit-error rate. In this parer, we implement the transmitter of this model. Because the power line is not designed for the data communication, we separated the signal generator circuit and the signal loading circuit so that minimized noises from outside. Also, to make it easy on the experiments, most of process are performed by software. As a result, transmitting a high frequency signal on the power line made no effects on the electrical devices.

• Journal of Sensor Science and Technology
• /
• v.29 no.3
• /
• pp.180-186
• /
• 2020

In this study, we applied edge-pulse modulation to prevent the flicker of light-emitting diode (LED) light in a visible light identification system. In the visible light transmitter, positive pulses were transmitted at the edges of the low-to-high transition points, and negative pulses were transmitted at the edges of the high-to-low transition points of the non-return-to-zero (NRZ) data waveforms. In the visible light receiver, the NRZ waveforms were regenerated by making low-to-high and high-to-low transitions at the point of the positive and negative pulses, respectively. This method has two advantages. First, it ensures that the LED light is flicker-free because the average optical power of the LED was kept constant during data transmission in the transmitter. Second, the 120 Hz optical noise from the adjacent lighting lamps was easily cut off using a simple RC-high pass filter in the receiver.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.1
• /
• pp.59-67
• /
• 2007

This paper presents a low power dual-level low voltage differential signaling (DLVDS) technique using current source switching for LCD driver ICs in portable products. The transmitter makes dual level signal that has two different level signal 400mVpp and 250mVpp while keeping the advantages of LVDS. The decoding circuit recovers the primary signal from DLVDS. The low power DLVDS is implemented using a $0.25{\mu}m$ CMOS process under 2.5V supply. The proposed circuit shows 800Mbps/2-line data rate and 9mW, 11.5mW power consumptions in transmitter and receiver, respectively. The proposed DLVDS scheme reduce power consumption dramatically compare with conventional one.

• Journal of Korea Society of Industrial Information Systems
• /
• v.18 no.5
• /
• pp.25-32
• /
• 2013

A 1.8V 2-Gb/s scalable low voltage signaling (SLVS) transmitter (TX) is designed for mobile applications requiring high speed and low power consumption. It consists of 4-lane TX for data transmission, 1-lane TX for a source synchronous clocking, and a 8-phase clock generator. The proposed SLVS TX has the scaling voltage swing from 50 mV to 650 mV and supports a high speed (HS) mode and a low power (LP) mode. An output impedance calibration scheme for the SVLS TX is proposed to improve the signal integrity. The proposed SLVS TX is implemented by using a 0.18-${\mu}m$ 1-poly 6-metal CMOS with a 1.8 V supply. The simulated data jitter of the implemented SLVS TX is about 8.04 ps at the data rate of 2-Gb/s. The area and power consumption of the 1-lane of the proposed SLVS TX are $422{\times}474{\mu}m^2$ and 5.35 mW/Gb/s, respectively.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.16 no.4
• /
• pp.1330-1350
• /
• 2022

As a preprocessing operation of transmitter antennas, the hybrid precoding is restricted by the limited computing resources of the transmitter. Therefore, this paper proposes a novel hybrid precoding that guarantees the communication efficiency with low complexity and a fast computational speed. First, the analog and digital precoding matrix is derived from the maximum eigenvectors of the channel matrix in the sub-connected architecture to maximize the communication rate. Second, the extended power iteration (EPI) is utilized to obtain the maximum eigenvalues and their eigenvectors of the channel matrix, which reduces the computational complexity caused by the singular value decomposition (SVD). Third, the Aitken acceleration method is utilized to further improve the convergence rate of the EPI algorithm. Finally, the hybrid precoding based on the EPI method and the Aitken acceleration algorithm is evaluated in millimeter-wave (mmWave) massive multiple-input and multiple-output (MIMO) systems. The experimental results show that the proposed method can reduce the computational complexity with the high performance in mmWave massive MIMO systems. The method has the wide application prospect in future wireless communication systems.

• Proceedings of the IEEK Conference
• /
• 2003.11c
• /
• pp.281-284
• /
• 2003

Multi-code CDMA is an appropriate scheme for transmitting high rate data. However, dynamic range of the signal is large, and power amplifier with good linearity is required. Code select CDMA (CS/CDMA) is a variation of multi-code CDMA scheme that ensures constant amplitude transmission. In CS/CDMA input data selects multiple orthogonal codes, and sum of these selected codes are MPSK modulated to convert multi-level symbol into different carrier phases. CS/CDMA system employs level clipping to limit the number of levels at the output symbol to avoid hish density of signal constellation. In our previous work we showed that by encoding input data of CS/CDMA amplitude of the output symbol can be made constant. With this coding scheme, level clipping is not necessary and the output signal can be BPSK modulated for transmission. In this paper we show that the constant amplitude coded(CA-) CS/CDMA transmitter can be implemented using only logic gates, and the hardware complexity is very low. In the proposed transmitter architecture there is no apparent redundant encoder block which plays a major role in the constant amplitude coded CS/CDMA.