• Title/Summary/Keyword: low power transmitter

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An Infrared Communication Module for the Enhancement of Hearing Aids (보청기 성능 향상을 위한 적외선 통신 모듈)

  • Park, Seong Mo
    • Smart Media Journal
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    • v.7 no.3
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    • pp.29-34
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    • 2018
  • This paper presents a study on adapting optical communication technology using infrared ray for the enhancement of hearing aids in noisy environment. The transmitter module containing microphone and infrared ray-emitting diode converts audio signal to infrared optical signal and sends it out in the air. The receiver module located in a distance receives the infrared signal, converts it to electrical signal, and transfers it to an input of a digital hearing aid. Especially, the receiver module needs to be small, low voltage, and consume low power since it will be attached to hearing aids. Experiments with applying infrared communication technology of digital modulation method and analog non-modulation method show that the analog non-modulation method is adequate for infrared communication of approximately 5m distance indoor. Prototypes of transmitter module and receiver module were manufactured, and internal parameters of the digital hearing aid were adjusted to confirm normal transmit-receive operation of audio signals.

Korea Red Ginseng Alters Electroencephalogram Spectra of Sleep-Wake Stage in Rats

  • Ma, Yuan;Eun, Jae-Soon;Cheong, Jae-Hoon;Rhee, Dong-Kwon;Hong, Jin-Tae;Oh, Ki-Wan
    • Journal of Ginseng Research
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    • v.32 no.3
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    • pp.220-225
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    • 2008
  • The present investigation was performed to evaluate the homeostatic regulation of sleep architecture by the ethanol extract of Korea red ginseng (KRG), since the available data were often controversial. In addition, it was also interested in whether the sleep-wake stages were differently affected by low and high doses of KRG. Each adult Wistar male rat was implanted with a transmitter for recording EEG and activity via telemetry. After one week of surgery, polygraphic signs of undisturbed sleep-wake activities were recorded for 12 h (between 9:00 am and 9:00 pm) after KRG administration. KRG (10 and 100 mg/kg) increased non-rapid eye movement (NREM) sleep as well as total sleep. The total percentages of wakefulness were decreased comparably. KRG (10 mg/kg) decreased the power density of the ${\delta}-wave$ (0.75-4.5 Hz) and increased ${\alpha}-wave$ (8.0-13.0 Hz) in the NREM and rapid eye movement (REM) sleep. KRG also decreased ${\delta}-wave$ power density in wake time. However, KRG (100 mg/kg) increased ${\delta}-wave$ and decreased ${\theta}-wave$ (5.0-9.0 Hz) power density in wake time, while showed little effect on the power density in NREM and REM sleep. In conclusion, low and high doses of KRG increase spontaneous sleep and NREM sleep and differently regulate the EEG spectra in REM and NREM sleep.

Digital Low-Power High-Band UWB Pulse Generator in 130 nm CMOS Process (130 nm CMOS 공정을 이용한 UWB High-Band용 저전력 디지털 펄스 발생기)

  • Jung, Chang-Uk;Yoo, Hyun-Jin;Eo, Yun-Seong
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.23 no.7
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    • pp.784-790
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    • 2012
  • In this paper, an all-digital CMOS ultra-wideband(UWB) pulse generator for high band(6~10 GHz) frequency range is presented. The pulse generator is designed and implemented with extremely low power and low complexity. It is designed to meet the FCC spectral mask requirement by using Gaussian pulse shaping circuit and control the center frequency by using CMOS delay line with shunt capacitor. Measurement results show that the center frequency can be controlled from 4.5 GHz to 7.5 GHz and pulse width is 1.5 ns and pulse amplitude is 310 mV peak to peak at 10 MHz pulse repetition frequency(PRF). The circuit is implemented in 0.13 um CMOS process with a core area of only $182{\times}65um^2$ and dissipates the average power of 11.4 mW at an output buffer with 1.5-V supply voltage. However, the core consumes only 0.26 mW except for output buffer.

A Modified Method Based on the Discrete Sliding Norm Transform to Reduce the PAPR in OFDM Systems

  • Salmanzadeh, R.;Mozaffari Tazehkand, B.
    • ETRI Journal
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    • v.36 no.1
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    • pp.42-50
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    • 2014
  • Orthogonal frequency division multiplexing (OFDM) is a modulation technique that allows the transmission of high data rates over wideband radio channels subject to frequency selective fading by dividing the data into several narrowband and flat fading channels. OFDM has high spectral efficiency and channel robustness. However, a major drawback of OFDM is that the peak-to-average power ratio (PAPR) of the transmitted signals is high, which causes nonlinear distortion in the received data and reduces the efficiency of the high power amplifier in the transmitter. The most straightforward method to solve this problem is to use a nonlinear mapping algorithm to transform the signal into a new signal that has a smaller PAPR. One of the latest nonlinear methods proposed to reduce the PAPR is the $L_2$-by-3 algorithm, which is based on the discrete sliding norm transform. In this paper, a new algorithm based on the $L_2$-by-3 method is proposed. The proposed method is very simple and has a low complexity analysis. Simulation results show that the proposed method performs better, has better power spectral density, and is less sensitive to the modulation type and number of subcarriers than $L_2$-by-3.

Clamping-diode Circuit for Marine Controlled-source Electromagnetic Transmitters

  • Song, Hongxi;Zhang, Yiming;Gao, Junxia;Zhang, Yu;Feng, Xinyue
    • Journal of Power Electronics
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    • v.18 no.2
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    • pp.395-406
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    • 2018
  • Marine controlled-source electromagnetic transmitters (MCSETs) are important in marine electromagnetic exploration systems. They play a crucial role in the exploration of solid mineral resources, marine oil, and gas and in marine engineering evaluation. A DC-DC controlled-source circuit is typically used in traditional MCSETs, but using this circuit in MCSETs causes several problems, such as large voltage ringing of the high-frequency diode, heating of the insulated-gate bipolar transistor (IGBT) module, high temperature of the high-frequency transformer, loss of the duty cycle, and low transmission efficiency of the controlled-source circuit. This paper presents a clamping-diode circuit for MCSET (CDC-MCSET). Clamping diodes are added to the controlled-source circuit to reduce the loss of the duty ratio and the voltage peak of the high-frequency diode. The temperature of the high-frequency diode, IGBT module, and transformer is decreased, and the service life of these devices is prolonged. The power transmission efficiency of the controlled-source circuit is also improved. Saber simulation and a 20 KW MCSET are used to verify the correctness and effectiveness of the proposed CDC-MCSET.

Performance Analysis of M-ary Optical Communication over Log-Normal Fading Channels for CubeSat Platforms

  • Lim, Hyung-Chul;Yu, Sung-Yeol;Sung, Ki-Pyoung;Park, Jong Uk;Choi, Chul-Sung;Choi, Mansoo
    • Journal of Astronomy and Space Sciences
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    • v.37 no.4
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    • pp.219-228
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    • 2020
  • A CubeSat platform has become a popular choice due to inexpensive commercial off-the-shelf (COTS) components and low launch cost. However, it requires more power-efficient and higher-data rate downlink capability for space applications related to remote sensing. In addition, the platform is limited by the size, weight and power (SWaP) constraints as well as the regulatory issue of licensing the radio frequency (RF) spectrum. The requirements and limitations have put optical communications on promising alternatives to RF communications for a CubeSat platform, owing to the power efficiency and high data rate as well as the license free spectrum. In this study, we analyzed the performance of optical downlink communications compatible with CubeSat platforms in terms of data rate, bit error rate (BER) and outage probability. Mathematical models of BER and outage probability were derived based on not only the log-normal model of atmospheric turbulence but also a transmitter with a finite extinction ratio. Given the fixed slot width, the optimal guard time and modulation orders were chosen to achieve the target data rate. And the two performance metrics, BER and outage data rate, were analyzed and discussed with respect to beam divergence angle, scintillation index and zenith angle.

A Reconfigurable CMOS Power Amplifier for Multi-standard Applications (다양한 표준에서 사용 가능한 CMOS 전력 증폭기)

  • Yun, Seok-Oh;Yoo, Hyung-Joun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.11
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    • pp.89-94
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    • 2007
  • For successful implementation of multi-standard transmitter, reconfigurable architecture and component design are essential. This paper presents a reconfigurable CMOS power amplifier designed CMOS 0.25 um process. Designed power amplifier can be operated at 0.9, 1.2, 1.75, and 1.85 GHz. Also, it can be used at 2.4 GHz by using bonding wire inductor. The interstage matching network is composed of two inductors and four switches, and operation frequency can be varied by controlling switches. Proposed power amplifier can be used as a power amplifier in low power applications such as ZigBee or Bluetooth application and used as a driver amplifier in high power application such as CDMA application. Designed power amplifier has 18.2 dB gain and 10.3 dBm output power at 0.9 GHz. Also, it represented 10.3 (18.1) dB gain and 5.2 (10) dBm output power at 1.75 (2.4) GHz.

Wireless Power Transmission High-gain High-Efficiency DC-AC Converter Using Harmonic Suppression Filter (고조파 억제 필터를 이용한 무선전력전송 고이득 고효율 DC-AC 변환회로)

  • Hwang, Hyun-Wook;Choi, Jae-Won;Seo, Chul-Hun
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.49 no.2
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    • pp.72-75
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    • 2012
  • In this paper, high-efficiency DC-AC converter is implemented for the wireless power transmission. The DC-AC converter is implemented by combining the oscillator and power amplifier. Because the conversion efficiency of wireless power transmitter is strongly affected by the efficiency of power amplifier, the high-efficiency power amplifier is implemented by using the Class-E amplifier structure. Also, because the output power of oscillator connected to the input stage of power amplifier is low, high-gain two-stages power amplifier using the drive amplifier is implemented to realize the high-output power DC-AC converter. The dual band harmonic suppression filter is implemented to suppress 2nd, 3rd harmonics of 13.56 MHz. The output power and conversion efficiency of DC-AC converter are 40 dBm and 80.2 % at the operation frequency of 13.56 MHz.

Performance Analysis of Equal Gain Transmission Technique for SC-FDMA System (SC-FDMA 시스템에서 동 이득 전송 기법의 성능분석)

  • Kim, Young-Ju;Li, Xun
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.46 no.9
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    • pp.1-7
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    • 2009
  • LTE-A (long term evolution advanced) uplink selected SC-FDMA (single carrier frequency division multiple access) to maintain low PAPR for a low price and tiny terminal. Recently, the application of codebook-based preceding to LIE-A uplink is discussed. This paper shows that PAPR can be increased when various preceding schems are applied to the SC-FDMA as an LTE-A uplink. When, considering nonlinear power amplifier model to the transmitter, BER performances of preceded schemes degrade. But equal gain transmission scheme does show very low PAPR. So the link-level performance of EGT is superior to those of any other preceding schemes. Computer simulations also confirm the anticipated link-level performances.

A 3.1 to 5 GHz CMOS Transceiver for DS-UWB Systems

  • Park, Bong-Hyuk;Lee, Kyung-Ai;Hong, Song-Cheol;Choi, Sang-Sung
    • ETRI Journal
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    • v.29 no.4
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    • pp.421-429
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    • 2007
  • This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

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