• 전력전자학회논문지
• /
• 제4권5호
• /
• pp.423-432
• /
• 1999

This paper proposes a 12­pulse diode rectifier system with low kVA components suitable for powering switch mode power supplies or ac/dc converter applications. The proposed 12-pulse system employs a polyphase transformer, a zero sequence blocking transformer (ZSBT) in the dc link, and an interphase transformer. Results produce near equal leakage inductance in series with each diode rectifier bridge ensuring equal current sharing and performance improvements, The utility input currents and the voltage across the ZSBT are analyzed the kVA rating of each component in the proposed system is computed. The 5th , 7th , 17th and 19th harmonics are eliminated in the input line currents resulting in clean input power. The dc link voltage magnitude generated by the proposed rectifier system is nearly identical to a conventional to a conventional 6-pulse system. The proposed system is suitable to retrofit applications as well as in new PWM drive systems. Simulation and experimental results from a 208V , 10kVA system are shown.

• 전력전자학회논문지
• /
• 제7권6호
• /
• pp.587-595
• /
• 2002

최근 배터리, 태양전지, 연료전지 등의 전원으로 구동되는 전기자동차에 대한 관심이 커지고 있다. 그런데, 이와 같은 전원들의 단위전지 전압은 자동차의 인버터를 구동하기에는 너무 낮기 때문에 수많은 단위전지를 직렬로 연결하여 사용해야하며, 이로 인해 전원의 구조가 복잡해지는 문제가 있다. 본 논문에서는 전기자동차의 응용을 위해 비교적 낮은 전원전압을 충분히 높은 안정된 직류 링크전압으로 바꾸어주는 고효율 대용량 승압 컨버터를 제안하고 그 설계기준과 실험결과를 제시한다.

• Journal of Power Electronics
• /
• 제15권2호
• /
• pp.309-318
• /
• 2015

This study proposes a dual-output single-stage bridgeless single-ended primary-inductor converter (DOSSBS) that can completely remove the front-end full-bridge alternating current-direct current rectifier to accomplish power factor correction for universal line input. Without the need for bridge diodes, the proposed converter has the advantages of low component count and simple structure, and can thus significantly reduce power loss. DOSSBS has two uncommon output ports to provide different voltage levels to loads, instead of using two separate power factor correctors or multi-stage configurations in a single stage. Therefore, this proposed converter is cost-effective and compact. A magnetically coupled inductor is introduced in DOSSBS to replace two separate inductors to decrease volume and cost. Energy stored in the leakage inductance of the coupled inductor can be completely recycled. In each line cycle, the two active switches in DOSSBS are operated in either high-frequency pulse-width modulation pattern or low-frequency rectifying mode for switching loss reduction. A prototype for dealing with an $85-265V_{rms}$ universal line is designed, analyzed, and built. Practical measurements demonstrate the feasibility and functionality of the proposed converter.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제11권3호
• /
• pp.221-228
• /
• 2011

This paper describes 250-Mb/s fiber optic transmitter and receiver ICs for plastic optical fiber applications using a$ 0.18-{\mu}m$ CMOS technology. Simple signal and light detection schemes are introduced for power reduction in sleep mode. The transmitter converts non-return-to-zero digital data into 650-nm visible-red light signal and the receiver recovers the digital data from the incident light signal through up to 50-m plastic optical fiber. The transmitter and receiver ICs occupy only 0.62 $mm^2$ of area including electrostatic discharge protection diodes and bonding pads. The transmitter IC consumes 23 mA with 20 mA of LED driving currents, and the receiver IC consumes 16 mA with 4 mA of output driving currents at 250 Mb/s of data rate from a 3.3-V supply in active mode. In sleep mode, the transmitter and receiver ICs consume only 25 ${\mu}A$ and 40 ${\mu}A$, respectively.

• 전자공학회논문지D
• /
• 제35D권11호
• /
• pp.85-90
• /
• 1998

다중모드간섭 현상에 입각한 1 4 폴리머 광파워분할기를 설계, 제작하였다. 이 광파워분할기는 2차원 유한차분 빔전파방법을 사용하여 설계하였다. 코어와 클래딩 물질로 각각 Cyclotene-3022과 UV-15이 사용되었고, 반응이온식각 공정에 의해 제작되었다. 제작된 1 4 광파워분할기의 각 출구에서의 측정된 광출력비는 TE모드에서 0.93 : 1.00 : 0.93 : 0.90, TM모드에서 0.84 : 0.94 : 1.00 : 0.83 이었다. 다중모드간섭 현상을 이용한 1 4 광파워분할기는 소자의 길이가 작고, 편광에 따른 의존도가 작은 장점이 있다.

• 대한전자공학회논문지SD
• /
• 제48권1호
• /
• pp.7-13
• /
• 2011

60GHz 대역 wireless personal area network(WPAN)을 위한 QPSK 복조기를 보인다. Mixed-mode QPSK 복조방식을 이용하여 전력소모와 면적을 줄였다. 설계된 회로는 60nm CMOS Logic 공정을 통해 제작되었으며, 4.8GHz 캐리어에서 최대 4.8Gb/s의 QPSK신호를 복조할 수 있다. 이 주파수에서, 복조기는 1.2V전원에서 54 mW를 소모하며, $150{\times}150{\mu}m^2$의 면적을 차지한다. 제작된 칩을 이용하여, 60GHz 링크에서 1.7GSymbol/s QPSK신호의 송선 및 복조 실험결과를 보인다.

• 전자공학회논문지C
• /
• 제36C권11호
• /
• pp.10-17
• /
• 1999

본 논문에서는 MOS 트랜지스터로만 이루어진 CMOS IADC(Current-mode Analog-to-Digital Converter)를 설계하였다. 각 단은 CSH(Current Sample-and-Hold)와 CCMP(Current Comparator)로 구성된 1.5-비트 비트 셀로 구성되었다. 비트 셀 전단은 CFT(Clock Feedthrough)가 제거된 9-비트 해상도의 차동 CSH를 배치하였고, 각 단 비트 셀의 ADSC(Analog-to-Digital Subconverter)는 2개의 래치 CCMP로 구성되었다. 제안된 IADC를 현대 0.65 ㎛ CMOS 파라미터로 ACAD 시뮬레이션 한 결과, 20 Ms/s에서 100 ㎑의 입력 신호에 대한 SINAD(Signal to Noise-Plus-Distortion)은 47 ㏈ SNR (Signal-to-Noise)는 50 ㏈(8-bit)을 얻었고 35.7 ㎽ 소비전력 특성을 나타냈다.

• Journal of Power Electronics
• /
• 제18권1호
• /
• pp.92-102
• /
• 2018

A sliding mode control (SMC) for servo motors based on the differential evolution (DE) algorithm, called DE-SMC, is proposed in this study. The parameters of SMC should be designed exactly to improve the robustness, realize the precision positioning, and reduce the steady-state speed error of the servo drive. The main parameters of SMC are optimized using the DE algorithm according to the speed feedback information of the servo motor. The most significant influence factor of the DE algorithm is optimization iteration. A suitable iteration can be achieved by the tested optimization process profile of the main parameters of SMC. Once the parameters of SMC are optimized under a convergent iteration, the system realizes the given performance indices within the shortest time. The experiment indicates that the robustness of the system is improved, and the dynamic and steady performance achieves the given performance indices under a convergent iteration when motor parameters mismatch and load disturbance is added. Moreover, the suitable iteration effectively mitigates the low-speed crawling phenomenon in the system. The correctness and effectiveness of DE-SMC are verified through the experiment.

• Transactions on Electrical and Electronic Materials
• /
• 제11권1호
• /
• pp.24-28
• /
• 2010

A simulation study of a current-mode direct current (DC)-DC buck converter is presented in this paper. The converter, with a fully integrated power module, is implemented by using sense method metal-oxide-semiconductor field-effect transistor (MOSFET) and bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. When the MOSFET is used in a current sensor, the sensed inductor current with an internal ramp signal can be used for feedback control. In addition, the BiCMOS technology is applied in the converter for an accurate current sensing and a low power consumption. The DC-DC converter is designed using the standard $0.35\;{\mu}m$ CMOS process. An off-chip LC filter is designed with an inductance of 1 mH and a capacitance of 12.5 nF. The simulation results show that the error between the sensing signal and the inductor current can be controlled to be within 3%. The characteristics of the error amplification and output ripple are much improved, as compared to converters using conventional CMOS circuits.

• Journal of Power Electronics
• /
• 제19권4호
• /
• pp.907-921
• /
• 2019

This paper presents two advanced hybrid pulse-width modulation (PWM) strategies for multilevel inverters (MLIs) that provide both common-mode voltage (CMV) elimination and current ripple reduction. The first PWM utilizes sequences that apply one switching state at the double ends of a half-carrier cycle. The second PWM combines the advantages of the former and an existing four-state PWM. Analyses of the harmonic characteristics of the two groups of switching sequences based on a general switching voltage model are carried out, and algorithms to optimize the current ripple are proposed. These methods are simple and can be implemented online for general n-level inverters. Using a three-level NPC inverter and a five-level CHB inverter, good performances in terms of the root mean square current ripple are obtained with the proposed PWM schemes as indicated through improved harmonic distortion factors when compared to existing schemes in almost the entire region of the modulation index. This also leads to a significant reduction in the current total harmonic distortion. Simulation and experimental results are provided to verify the effectiveness of the proposed PWM methods.