• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.423-424
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• 2011

This paper has proposed a 920 MHz RF front-end for IEEE 802.15.4g SUN (Smart Utility Network) systems. The proposed 920 MHz RF front-end consists of a driver amplifier, a low noise amplifier, and a RF switch. In the TX mode, the driver amplifier has been designed as a single-ended topology to remove a transformer which causes a loss of the output power from the driver amplifier. In addition, a RF switch is located in the RX path not the TX path. In the RX mode, the proposed low noise amplifier can provide a differential output signal when a single-ended input signal has been applied to. A LC resonant circuit is used as both a load of the drive amplifier and a input matching circuit of the low noise amplifier, reducing the chip area. The proposed 920 MHz RF Front-end has been implemented in a 0.18-um CMOS technology. It consumes 3.6 mA in driver amplifier and 3.1 mA in low noise amplifier from a 1.8 V supply voltage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.5
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• pp.251-259
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• 2014

In this paper, we propose Low Energy Service Discovery (LESD) protocol for common discovery mode of IEEE 802.15.8 Peer Aware Communications (PAC). In order to minimize power consumption, Basic Repetition Block (BRB) is defined. Device is able to select operating mode and synchronize other devices through it. Proposed MAC procedure is Carrier Sense Multiple Access with Collision Avoidance (CSMA/CA) based on overhearing technique. Even if device has not been received response signal since transmitted request signal, it is able to discover other devices of same group through the overhearing technique. IEEE 802.15.8 PAC has required that performances of common discovery mode are presented about discovered devices during the simulation time, discovery latency and average power consumption. By considering the number of devices per group and channel environment, two scenarios are evaluated through system level simulation and the simulation results of proposed scheme are compared with CSMA/CA in same simulation conditions. As a result, proposed scheme is able to get high energy efficiency of devices as well as increase the number of discovered devices during simulation time when the longer the number of devices is distributed over a limited area.

• The Journal of the Acoustical Society of Korea
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• v.41 no.3
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• pp.278-286
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• 2022

In this study, a 33-mode Free-Flooded Ring (FFR) transducer was designed to apply piezoelectric single crystal PIN-PMN-PT, which has high piezoelectric constants and electromechanical coupling coefficient. To ensure low-frequency high transmitting sensitivity characteristics with a small size of FFR transducer, the commercial FFR transducer based on piezoelectric ceramics was compared. To develop the FFR transducer with broadband characteristics, a piezoelectric segmented ring structure inserted with inactive elements was applied. The oil-filled structure was applied to minimize the change of acoustic characteristics of the ring transducer. It was verified that the transmitting voltage response, underwater impedance, and beam pattern matched the finite element numerical simulation results well through an acoustic test. The difference in the transmitting voltage response between the measured and the simulated results is about 1.3 dB in cavity mode and about 0.3 dB in radial mode. The fabricated FFR transducer had a higher transmitting voltage response compared to the commercial transducer, but the diameter was reduced by about 17 %. From this study, it was confirmed that the feasibility of a single crystal-applied FFR transducer with compact size and high-power characteristics. The effectiveness of the performance prediction by simulation was also confirmed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.55-55
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• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility (${\sim}900cm^2/Vs$). These electronic properties allow high breakdown voltage, high frequency, and high temperature operation compared to Silicon devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances. the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. In this paper, we report the effect of the interface states ($Q_s$) on the transient characteristics of SiC DMOSFETs. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. The result is a low-loss transient characteristic at low $Q_s$. Based on the simulation results, the DMOSFETs exhibit the turn-on time of 10ns at short channel and 9ns at without the interface charges. By reducing $SiO_2/SiC$ interface charge, power losses and switching time also decreases, primarily due to the lowered channel mobilities. As high density interface states can result in increased carrier trapping, or recombination centers or scattering sites. Therefore, the quality of $SiO_2/SiC$ interfaces is important for both static and transient properties of SiC MOSFET devices.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.2
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• pp.37-44
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• 2008

This paper presents a 5.8 GHz PLL using high-speed ring oscillator for WLAN. The proposed ring oscillator has been designed using the negative skewed delay scheme and for differential mode operation. Therefore, the oscillator is insensitive to power-supply-injected noise, and it has the merit of low 1/f noise because tail current sources are not used. The output frequency ranges from 5.13 to 7.04 GHz with the control voltage varing from 0 to 1.8 V. The proposed PLL circuits have been designed, simulated, and proved using 0.18 um 1.8 V TSMC CMOS library. At the operation frequency of 5.8 GHz, the locking time is 2.5 us and the simulated power consumption is 59.9 mW.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.3
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• pp.96-106
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• 2007

The terminal voltage of a synchronous generator is maintained by the field current control of excitation system. Generally AC/DC converter which is component of AVR(Automatic Voltage Regulator) system for excitation current control is connected to diode rectifier and DC/DC converter system. In the case of diode rectifier system of phase controlled converter as AC/DC converter have low power factor and harmonics of lower order in the line current. In this paper, two stage three phase PWM AC/DC converter is studied to solve these problems. The characteristics of a proposed converter reduces the harmonics and reactive power of the distribution line and has fast dynamic response in transient period using boost converter and current control mode buck converts. The proposed method is verified by the computer simulation and experimental results in prototype generation system.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.6
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• pp.83-88
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• 2017

In this paper, a 3-port waveguide circulator of Ka-band millimeter-wave for isolation between transmit channel and receive channel at high power transmit mode is designed and fabricated for the seeker of the guided missile and circulator performance is verified through the S-parameter, high power and operation temperature test. At the configuration design, interface design between a seeker antenna and the circulator is considered and half-height of standard waveguide is applied for minimum and light weight body. The shape of permanent magnet and ferrite is optimized by simulation and tuning dielectrics at each port are placed for the best performance. In Fc(center frequency)${\pm}1000MHz$, designed waveguide circulator has below -20 dB return loss, below 0.5 dB insertion loss and below -23 dB isolation. It is found that circulator characteristics is similar to design results.

• Journal of IKEEE
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• v.16 no.4
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• pp.335-342
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• 2012

This paper is studied on a new DCM-ZVS step up-down AC-DC converter of high performance, that is, high system efficiency and power factor correction (PFC). The switching devices in the proposed converter are operated by soft switching technique using a new quasi-resonant circuit, and are driven with discontinuous conduction mode (DCM) according to pulse width modulation (PWM). The quasi-resonant circuit uses a step up-down inductor and a loss-less snubber capacitor. The proposed converter with DCM also simplifies the requirement of control circuits and reduces the number of control components. The input AC current waveform in the proposed converter becomes a quasi-sinusoidal waveform proportional to the magnitude of input AC voltage under constant switching frequency. As a result, the proposed converter obtains low switching power loss and high efficiency, and its input power factor is nearly in unity. The validity of the analytical findings is confirmed by some computer simulation results and experimental results.

• Journal of Electrical Engineering and Technology
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• v.13 no.3
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• pp.1251-1264
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• 2018

The systematic and effective design method of a Class-D current-source resonant inverter for use in an induction cooker with zero-ripple line current is presented. The design procedure is based on the principle of the Class-D current-source resonant inverter with a simplified load network model that is a parallel equivalent circuit. An induction load characterization is obtained from a large-signal excitation test-bench based on parallel load network, which is the key to an accurate design for the induction cooker system. Accordingly, the proposed scheme provides a systematic, precise, and feasible solution than the existing design method based on series-parallel load network under low-signal excitation. Moreover, a zero-ripple condition of utility-line input current is naturally preserved without any extra circuit or control. Meanwhile, a differential-mode input electromagnetic interference (EMI) filter can be eliminated, high power quality in utility-line can be obtained, and a standard-recovery diode of bridge-rectifier can be employed. The step-by-step design procedure explained with design example. The devices stress and power loss analysis of induction cooker with a parallel load network under large-signal excitation are described. A 2,500-W laboratory prototype was developed for $220-V_{rms}/50-Hz$ utility-line to verify the theoretical analysis. An efficiency of the prototype is 96% at full load.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1877-1886
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• 2010

In this paper, we design a redundancy control circuit for 1T-SRAM repair using electrical fuse programming. We propose a dual port eFuse cell to provide high program power to the eFuse and to reduce the read current of the cell by using an external program supply voltage when the supply power is low. The proposed dual port eFuse cell is designed to store its programmed datum into a D-latch automatically in the power-on read mode. The layout area of an address comparison circuit which compares a memory repair address with a memory access address is reduced approximately 19% by using dynamic pseudo NMOS logic instead of CMOS logic. Also, the layout size of the designed redundancy control circuit for 1T-SRAM repair using electrical fuse programming with Dongbu HiTek's $0.11{\mu}m$ mixed signal process is $249.02 {\times}225.04{\mu}m^{2}$.