• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.501-512
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• 2018

Radio frequency identification (RFID) sensor tag provides several advantages including battery-less operation and low cost, which are suitable for long-term monitoring. This paper presents a self-powered RFID temperature sensor tag for online temperature monitoring in substation. The proposed sensor tag is used to measure and process the temperature of high voltage equipments in substation, and then wireless deliver the data. The proposed temperature sensor employs a novel phased-locked loop (PLL)-based architecture and can convert the temperature sensor in frequency domain without a reference clock, which can significantly improve the temperature accuracy. A two-stage rectifier adopts a series of auxiliary floating rectifier to boost its gate voltage for higher power conversion efficiency. The sensor tag chip was fabricated in TSMC $0.18{\mu}m$ 1P6M CMOS process. The measurement results show that the proposed temperature sensor tag achieve a resolution of $0.15^{\circ}C$/LSB and a temperature error of $-0.6/0.7^{\circ}C$ within the range from $-30^{\circ}C$ to $70^{\circ}C$. The proposed sensor tag achieves maximum communication distance of 11.8 m.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.486-495
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• 2006

In this paper, a low-power 1Kb synchronous EEPROM is designed with flash cells for passive UHF RFID tag chips. To make a low-power EEPROM, four techniques are newly proposed. Firstly, dual power supply voltages VDD(1.5V) and VDDP(2.5V), are used. Secondly, CKE signal is used to remove switching current due to clocking of synchronous circuits. Thirdly, a low-speed but low-power sensing scheme using clocked inverters is used instead of the conventional current sensing method. Lastly, the low-voltage, VDD for the reference voltage generator is supplied by using the Voltage-up converter in write cycle. An EEPROM is fabricated with the $0.25{\mu}m$ EEPROM process. Simulation results show that power dissipations are $4.25{\mu}W$ in the read cycle and $25{\mu}W$ in the write cycle, respectively. The layout area is $646.3\times657.68{\mu}m^2$.

• Journal of Korea Multimedia Society
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• v.23 no.3
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• pp.440-446
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• 2020

The application field of smart terminals is increasing and its application is also spreading in the defense field. The use of smart terminal based map application is very important in battle fields. The problem is that the communication infrastructure is easy to collapse and the use of GPS is usually disturbed. In this paper, we studied the maps stored in the QR tag at the battle field. The problem is to abstract the map information so that it can be stored in the small QR tag. We have abstracted path information on a vector basis and require only a small amount of data compared to imaged path information. We analyzed the amount of data generated by the abstraction and mathematically analyzed the boundary where the amount does not exceed the capacity limit of the QR tag. Our research can be applied not only to battlefields, but also to disaster / disaster scenes, or in environments with difficult Internet communications, such as mountainous areas.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.19 no.3
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• pp.61-72
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• 2009

To guarantee security between the tag and back-end server and implementation efficiency in low power tag, we propose two typed mutual authentication protocols in RFID system. One is static-ID authentication scheme which is well suitable in distributed server environments. The other is dynamic-ID scheme which is additively satisfied forward security. In proposed scheme, it does not need any random number generator in tag and requires only one(maximally three) hash operation(s) in tag or server to authenticate each other. Furthermore, we implement the proposed schemes in RFID smart card system and verify its normal operations.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.345-348
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• 2001

In this paper, we present a effective low-power technique which can reduce significantly the switching activity in instruction address bus, pipeline and I-cache. Using this method, named Guarded Operation, we has implemented address register. address bus architecture without complex hardware and designed loop buffer without tag. These architectures reduce 67% of switching activity with little overhead and also increase instruction-fetch performance.

• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.1
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• pp.25-32
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• 2014

In this paper, we proposed a partial-way set associative cache memory with an effective memory access time and low energy consumption. In the proposed set-associative cache memory, it is allowed to access only a 2-ways among 4-way at a time. Choosing ways to be accessed is made dynamically via the least significant two bits of the tag. The chosen 2 ways are sequentially accessed by the way selection bits that indicate the most recently referred way. Therefore, each entry in the way has an additional bit, that is, the way selection bit. In addition, instead of the 4-way LRU or FIFO algorithm, we can utilize a simple 2-way replacement policy. Simulation results show that the energy*delay product can be reduced by about 78%, 14%, 39%, and 15% compared with a 4-way set associative cache, a sequential-way cache, a way-tracking cache, and a way cache respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.12
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• pp.2366-2373
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• 2007

In this paper, a low-power and small-area asynchronous 1 kilobit EEPROM for passive UHF RFID tag chips is designed with $0.18{\mu}m$ EEPROM cells. As small area solutions, command and address buffers are removed since we design asynchronous I/O interface and data output buffer is also removed by using separate I/O. To supply stably high voltages VPP and VPPL used in the cell array from low voltage VDD, Dickson charge pump is designed with schottky diodes instead of a PN junction diodes. On that account, we can decrease the number of stages of the charge pump, which can decrease layout area of charge pump. As a low-power solution, we can reduce write current by using the proposed VPPL power switching circuit which selects each needed voltage at either program or write mode. A test chip of asynchronous 1 kilobit EEPROM is fabricated, and its layout area is $554.8{\times}306.9{\mu}m2$., 11% smaller than its synchronous counterpart.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.4
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• pp.3-12
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• 2006

RFID (Radio Frequency Identification) system is expected to play a critical role providing widespread services in the ubiquitous period. However, widespread use of RFID tags may create new threats to the privacy of individuals such as information leakage and traceability. It is difficult to solve the privacy problems because a tag has the limited computing power that is not the adequate resource to support the general encryption. Although the scheme of [2] protects the consumer privacy using an external agent, a tag should compute exponential operation needed high cost. We propose Self Re-Encryption Protocol (SREP) which provides song privacy without assisting of any external agent. Our SREP is well suitable to low-cost RFID system since it only needs multiplication and exclusive-or operation.

• The KIPS Transactions:PartA
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• v.14A no.1 s.105
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• pp.55-62
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• 2007

Uptime of embedded processors for mobile devices are dependent on battery consumption. Especially the large portion of power consumption is known to be due to cache management in embedded processors. This paper proposes an energy efficient data cache structure for high performance embedded processors. High performance prefetching data cache issues prefetching instructions before issuing demand-fetch instructions based on reference predictions. These prefetching instruction bring reduction on memory delay by improving cache hit ratio, but on the other hand those increase energy consumption in proportion to the number of prefetching instructions. In this paper, we adopt tag history table on prefetching data cache for reducing energy consumption by minimizing parallel tag comparison. Experimental results show the proposed data cache improves performance on energy consumption as well as memory delay.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7B
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• pp.1342-1350
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• 1999

In this paper, we have developed and analyzed the 2.45GHz microwave RFID system. Which is composed tag and interrogator using custom IC, and we have made the software driving the hardware for the bidirectional data transmission method. Using 3.6V power supply was used, the optimal identification range in the information transmission of the designed microwave RFID system operating at 9,600bps was l0m. In the control circuit of the tag, the low current consumption of 15$mutextrm{A}$ and the tag data transmission rate of 90% when the moving velocity was 80km/h.