• Journal of Electrical Engineering and Technology
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• v.11 no.6
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• pp.1656-1663
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• 2016

A capacitive wireless power transfer (C-WPT) system uses an electric field to transmit power through a physical isolation barrier which forms a pair of ac link capacitors between the metal plates. However, the physical dimension and low dielectric constant of the interface medium severely limit the effective link capacitance to a level comparable to the main switch output capacitance of the transmitting circuit, which thus narrows the soft-switching range in the light load condition. Moreover, by fundamental limit analysis, it can be proved that such a low link capacitance increases operating frequency and capacitor voltage stress in the full load condition. In order to handle these problems, this paper investigates optimal design of double matching transformer networks for C-WPT. Using mathematical analysis with fundamental harmonic approximation, a design guideline is presented to avoid unnecessarily high frequency operation, to suppress the voltage stress on the link capacitors, and to achieve wide ZVS range even with low link capacitance. Simulation and hardware implementation are performed on a 5-W prototype system equipped with a 256-pF link capacitance and a 200-pF switch output capacitance. Results show that the proposed scheme ensures zero-voltage-switching from full load to 10% load, and the switching frequency and the link capacitor voltage stress are kept below 250 kHz and 452 V, respectively, in the full load condition.

• Proceedings of the KIEE Conference
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• 1999.07f
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• pp.2653-2655
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• 1999

A technique to suppress the low frequency ripple voltage of the DC output voltage in three-phase buck diode rectifiers is presented. A pulse frequency modulation method is employed to regulate the output voltage of the rectifier and guarantee zero-current switching of the switch over the wide operating range. The pulse frequency control method used in this paper shows generally good performance such as low THD of the input line current and unity power factor. In addition, the pulse frequency method can be effectively used to suppress the low frequency voltage ripple appeared in the dc output voltage. The proposed technique illustrates its validity and effectiveness through the respective simulations and experiments.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.63-70
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• 2014

A low-N phase-locked loop clock generator with frequency multiplier is proposed to improve phase noise characteristic. Delay-variance voltage converter (DVVC) generates output voltages according to the delay variance of delay stages in voltage controlled oscillator. The output voltages of average circuit with the output voltages of DVVC are applied to the delay stages in VCO to reduce jitter. The HSPICE simulation of the proposed phase-locked loop clock generator with a $0.18{\mu}m$ CMOS process shows an 11.3 ps of peak-to-peak jitter.

• Journal of Power Electronics
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• v.12 no.3
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• pp.377-386
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• 2012

An interleaved bridgeless buck-boost AC/DC converter is presented in this paper to achieve the characteristics of low conduction loss, a high power factor and low harmonic and ripple currents. There are only two power semiconductors in the line current path instead of the three power semiconductors in a conventional boost AC/DC converter. A buck-boost converter operated in the boundary conduction mode (BCM) is adopted to control the active switches to achieve the following characteristics: no diode reverse recovery problem, zero current switching (ZCS) turn-off of the rectifier diodes, ZCS turn-on of the power switches, and a low DC bus voltage to reduce the voltage stress of the MOSFETs in the second DC/DC converter. Interleaved pulse-width modulation (PWM) is used to control the switches such that the input and output ripple currents are reduced such that the output capacitance can be reduced. The voltage doubler topology is adopted to double the output voltage in order to extend the useable energy of the capacitor when the line voltage is off. The circuit configuration, principle operation, system analysis, and a design example are discussed and presented in detail. Finally, experiments on a 500W prototype are provided to demonstrate the performance of the proposed converter.

• Journal of Korea Society of Digital Industry and Information Management
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• v.10 no.1
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• pp.1-6
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• 2014

In this paper, we propose a CPLD low power algorithm considering the structure. The proposed algorithm is implemented CPLD circuit FC(Feasible Cluster) for generating a problem occurs when the node being split to overcome the area and power consumption can reduce the algorithm. CPLD to configure and limitations of the LE is that the number of OR-terms. FC consists of an OR node is divided into mainly as a way to reduce the power consumption with the highest number of output nodes is divided into a top priority. The highest number of output nodes with the highest number of switching nodes become a cut-point. Division of the node is the number of OR-terms of the number of OR-terms LE is greater than adding the input and output of the inverter converts the AND. Reduce the level, power consumption and area. The proposed algorithm to MCNC logic circuits by applying a synthetic benchmark experimental results of 13% compared to the number of logical blocks decreased. 8% of the power consumption results in a reduced efficiency of the algorithm represented been demonstrated.

• Journal of Power Electronics
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• v.18 no.1
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• pp.116-128
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• 2018

Conventionally, in order to reduce the ac components of the dc-link capacitors of the two-level Half-Bridge Voltage Source Inverter (HB-VSI), high dc-link capacitances are required. This necessitates the employment of short-lifetime and bulky electrolytic capacitors. In this paper, an analysis for the performance of low dc-link capacitances-based HB-VSI is presented to elucidate its ability to generate an enhanced fundamental output voltage magnitude without increasing the voltage rating of the involved switches. This feature is constrained by the load displacement factor. The introduced enhancement is due to the ac components of the capacitors' voltages. The presented approach can be employed for multi-phase systems through using multi single-phase HB-VSI(s). Mathematical analysis of the proposed approach is presented in this paper. To ensure a successful operation of the proposed approach, a closed loop current controller is examined. An expression for the critical dc-link capacitance, which is the lowest dc-link capacitance that can be employed for unipolar capacitors' voltages, is derived. Finally, simulation and experimental results are presented to validate the proposed claims.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.11
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• pp.948-952
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• 2007

In this study, a low temperature sintering multilayer piezoelectric transformer for a DC-DC converter was manufactured using $(Pb,Ca,Sr,)(Ti,Mn,Sb)O_3$ ceramics. Its electrical properties were investigated according to the variation in frequency and load resistance. The voltage step-up ratio of the multilayer piezoelectric transformer showed a maximum value at a resonant frequency of input part and increased with an increase of load resistance. The efficiency of the multilayer piezoelectric transformer showed the highest value at a load resistance of 17 $\Omega$. The output power was increased with increasing input voltage. Temperature increase of the multilayer piezoelectric transformer was increased with the increase of output power. At the load resistance of 17 $\Omega$, the multilayer piezoelectric transformer showed the temperature rises of about $20^{\circ}C$ at the output power of 18 W, and stable driving characteristics.

• Journal of Chest Surgery
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• v.40 no.9
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• pp.633-636
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• 2007

Coronary artery spasm immediately after the coronary artery bypass graft (CABG) surgery is rare but it can cause sudden and severe hypotension or a ventricular arrhythmia. We report a case of low cardiac output syndrome caused by a right coronary artery spasm following CABG that did not show any significant stenotic lesions on preoperative coronary angiography.

• Journal of Power Electronics
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• v.13 no.2
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• pp.197-205
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• 2013

In energy injection resonant AC-AC converters, due to the low frequency effect of the AC input envelope and the low energy injection losses requirement, the constant and steady control of the high frequency AC output envelope is still a problem that has not been solved very well. With the aid of system modeling, this paper analyzes the mechanism of the envelope pit on the resonant AC current. The computing methods for the critical damping point, the falling time and the bottom value of the envelope pit are presented as well. Furthermore, this paper concludes the stability precondition of the system AC output. Accordingly, an optimal control method for the AC output envelope is put forward based on the envelope prediction model. This control method can predict system responses dynamically under different series of control decisions. In addition, this control method can select best series of control decisions to make the AC output envelope stable and constant. Simulation and experimental results for a contactless power transfer system verify the control method.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.3
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• pp.69-80
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• 2015

This paper is writing about developing magnet power supply. It is very important for power supply to obtain output current in high precision and high stability. As a switching noise and a power noise are the cause of disrupting the stability of output current, to remove these at the front end, low pass filter with 300Hz cutoff frequency is designed and placed. And also to minimize switching noise of the current into magnet and to stop abrupt fluctuations, output filter should be designed, when doing this, we design it by considering load has high value inductance. As power supply demands the stability of less than 5ppm, high precision 24bit(300nV/bit) analog digital converter is needed. As resolving power of 24bit(300nV/bit) analog digital converter is high, it is also very important to design the input stage of analog digital converter. To remove input noise, 4th order low pass filter is composed. Due to the limitation of clock, to minimize quantization error between 15bit DPWM and output of ADC having 24bit resolving power, ${\Sigma}-{\Delta}$ modulation is used and bit contracted DPWM is constituted. And before implementing, to maximize efficiency, simulink is used.