• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.979-982
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• 2003

Due to the differential transmission technique and low voltage swing, LVDS has been widely used for high speed transmission with low power consumption. This paper presents the design and implementation of interface circuits for 1.5Gb/s operation in 0.35um CMOS technology. The interface circuit ate fully compatible with the low-voltage differential signaling(LVDS) standard. The LVDS proposed in this paper utilizes a sense amplifiers instead of the conventional differential pre-amplifier, which provides a 1.5Gb/s transmission speed with further reduced driver output voltage. Furthermore, the reduced driver output voltage results in reducing the power consumption.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2002년도 종합학술발표회 논문집 Vol.12 No.1
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• pp.16-20
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• 2002

This paper describes the resistive FET mixer with low IF for the 4-Ch DBF(Digital Beam Forming) receiver with LNA(Low Noise Amplifier). This DBF receiver based on the direct conversion method is generally suitable for high-speed wireless mobile communications. A radio frequency(RF), a local oscillator(LO) and an intermediate frequency(IF) considered in this research are 2.09 ㎓, 2.08 ㎓ and 10㎒, respectively. The RF input power, LO input power and Vgs are used -10㏈m, 6㏈m and -0.4 V, respectively. In the 4-Ch resistive FET mixer with LNA, the measured IF and harmonic components of 10㎒, 20㎒, 2.09㎓ and 4.17㎓ are about -12.5 ㏈m, -57㏈m, -40㏈m and -54㏈m, respectively. The IF output power observed at each channel of 10㎒ is about -12.5㏈m and it is higher 27.5 ㏈m than the maximum harmonic component of 2.09㎓. Each IF output spectrum of the 4-Ch is observed almost same value and it shows a good agreement with the prediction.

• 전자공학회논문지D
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• 제34D권9호
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• pp.1-6
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• 1997

A transmission type phase shift attenuator has a poor reflection characteristics at an output port. And that is controlled by the current, its dynamic rnage decreases due to the current limitation. In this paper, to avoid such disadvantages, a reflection type low phase shift attenuator has been designed and measured. As a result, at a center frequency (1855MHz), the sreflection type low pahse shift attenuator has an attenuation of 30dB, within the limit of 3 phase shift and less than -17dB reflection characteristics at both input and output ports. And it demonstrates the peformance of the reflection type low phase shift attenuator is better than the transmission type phase shift attenuator with the same measurement specifications.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 추계종합학술대회 B
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• pp.890-893
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• 2008

In this paper, we present a low complexity modified multi-level sphere decoder (SD) for multiple-input multiple-output (MIMO) systems employing quadrature amplitude modulation (QAM) signals. The proposed decoder, exploiting the multi-level structure of the QAM signal scheme, first decomposes the high-level constellation into low-level 4-QAM constellations, so-called sub-constellations. Then, it deploys SD in the sub-constellations in parallel. In addition, in the searching stage, it uses the optimal low-complexity sort method. Computer simulation results show that the proposed decoder can provide near optimal maximum-likelihood (ML) performance while it significantly reduces the computational load.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.221-224
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• 2004

This paper proposed an ultra low-power CMOS exponential voltage-mode circuit using the Pseudo-exponential function for realizing the exponential characteristics. The proposed circuit provides high dB-linear output voltage range at low-voltage applications. In a $0.25\;\mu m$ CMOS process, the simulations show more than 35 dB output voltage range and 26 dB with the linearity error less than $\pm0.5\;dB.$ The average current consumption is less than 80 uA. The proposed circuit can be used for the design of an extremely low-power variable gain amplifier (VGA) and automatic gain control (AGC).

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2002년도 추계종합학술대회
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• pp.462-466
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• 2002

본 논문에서는 8Bit MPU를 이용한 신경자극 치료장치가 설계되었다. 개발되고 있는 시스템은 저전력 MPU와 전압 boosting회로, 과전류 감시 및 이상전류 보정회로, 펄스의 상태를 알려주는 LED display 및 BUTTO과 펄스를 우리 몸에 전달시켜주는 Pad로 이루어져있다. 입력된 9V의 전압은 전압 boosting회로를 통해 120V까지 승압된다. 펄스는 단상 직사각형파, 대칭성 이상파, 교대 대칭성 이상파등의 형태로 우리 몸에 입력되어 근육의 수축과 이완을 시켜주는 알고리즘을 적용하였다.

• Journal of the Korean Physical Society
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• 제73권12호
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• pp.1889-1894
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• 2018

An innovative small-scale piezoelectric energy harvester has been proposed to gather wind energy. A conventional horizontal-axis wind power generation has a low generating efficiency at low wind speed. To overcome this weakness, we designed a piezoelectric windmill optimized at low-speed wind. A piezoelectric device having high energy conversion efficiency is used in a small windmill. The maximum output power of the windmill was about 3.14 mW when wind speed was 1.94 m/s. Finally, the output power and the efficiency of the system were compared with a conventional wind power system. This work will be beneficial for the piezoelectric energy harvesting technology to be applied to the real world such as wireless sensor networks (WSN).

• 한국정보전자통신기술학회논문지
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• 제13권2호
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• pp.123-128
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• 2020

본 논문에서는 주파수 변화 감지 회로 (FVSC : frequency variation sensing circuit)를 포함하는 부궤환 루프를 가지는 저잡음 위상고정루프를 제안하였다. 위상 고정 상태에서 전압제어발진기의 출력주파수가 변화할 때 주파수 변화 감지 회로는 루프 필터의 커패시터의 전하량을 조절하여 제안한 위상고정루프의 위상잡음과 지터 특성을 개선할 수 있다. 위상고정루프의 출력 주파수가 증가하면 주파수 변화 감지 회로가 루프 필터 커패시터 전하를 감소시킨다. 이는 루프필터 출력 전압을 하강하게 하여 위상고정루프 출력 주파수가 하강하게 된다. 추가된 부궤환 루프는 제안한 위상고정루프의 위상잡음 특성을 더욱 더 좋게 한다. 주파수 변화 감지 회로에 사용된 커패시터 크기는 영점을 결정하는 루프 필터 커패시터 크기와 비교하여도 아주 작은 크기이어서 칩 크기에 영향을 미치지 않는다. 제안된 저잡음 위상고정루프는 1.8V 0.18㎛ CMOS 공정을 이용하여 설계되었다. 시뮬레이션 결과는 273fs 지터와 1.5㎲ 위상고정시간을 보여주었다.

• Journal of Chest Surgery
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• 제25권3호
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• pp.232-239
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• 1992

Acute renal failure is a well known serious complication following open heart surgery and is associated with a significant increase in morbidity and mortality rate. From 1984 to 1990, 33 patients who had acute renal failure following cardiopulmonary bypass received renal replacement therapy. PD[Peritonial dialysis] was employed in 11 patients and CAVH[continous arteriovenous hemofiltration] was employed in 22 patients. Their age ranged from 3 months to 64 years[mean 25.5$\pm$7.8 years]. The disease entities included congenital cardiac anomaly in 18, valvular heart disease in 15 and aorta disease in 2 cases. Low cardiac output was thought as a primary cause of ARF except two redo valve cases who showed severe Aemolysis k depressed renal function preoperatively. Mean serum BUN and creatinine level at the onset renal replacement therapy were 65$\pm$8 mg/dl and 3.5$\pm$0.4 mg/dl respectively, declining only after reaching peak level 7&10 days following the onset of therapy. Overall hospital mortality was 72.7%[24/33]; 81%[9/11] in PD group and 68.2% [15/22] in CAVH group respectively. The primary cause of death was low cardiac output & hemodynamic depression in all the cases. The fatal complications included multiorgan failure in 7, disseminated intravascular coagulation and sepsis in 6, neurologic damage in 4 and mediastinitis in 3 cases. No measurable differences were observed between CAVH and PD group upon consequence of acute renal failure and disease per se. The age at operation, BUN/Cr level at the onset of bypass and highest BUN/Cr level and the consequence of low output status were regarded as important risk factors, determining outcome of ARF and success of renal replacement therapy. Thus, we concluded that althoght the prognosis is largely determined by severity of low cardiac output status and other organ complication, early institution of renal replacement therapy with other intensive supportive measures could improve salvage rate in established ARF patients following CPB.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.948-950
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• 2003

In this literature, the CMOS current mode fout quadrant differentiator circuit is proposed. The implementation is base on an appropriate input stage that converts the input current into a compressed voltage at the input capacitor ($C_{gs}$) of the CMOS driver circuit. This input voltage use as the control output current which flow to the output node by passing through a MOS active load and use it as the feedback voltage to the input node. Simulation results with level 49 CMOS model of MOSIS are given to demonstrate the correct operation of the proposed configuration. But the gain of the circuit is too low so the output differentiate current also low. The proposed differentiator is expected to find several applications in analog signal processing system.